E_Future 发表于 2009-9-11 15:39:00

[求助]【紧急】OrCAD原理图,只要删除某一些网络,就会报错,这是什么原因?

<p>报错提示如下:而且就这一个错误,这是什么原因呢?</p><p>软件是OrCAD+Allegro 15.7 s007,如果用Cadence 16.0则没此问题。</p><p>------ Summary Statistics ------</p><p>#1 ERROR(102) Run stopped because errors were detected</p><p><br/>netrev run on Sep 11 15:29:24 2009<br/>&nbsp;&nbsp; DESIGN NAME : '01'<br/>&nbsp;&nbsp; PACKAGING ON May 28 2006 22:05:31</p><p>&nbsp;&nbsp; COMPILE 'logic'<br/>&nbsp;&nbsp; CHECK_PIN_NAMES OFF<br/>&nbsp;&nbsp; CROSS_REFERENCE OFF<br/>&nbsp;&nbsp; FEEDBACK OFF<br/>&nbsp;&nbsp; INCREMENTAL OFF<br/>&nbsp;&nbsp; INTERFACE_TYPE PHYSICAL<br/>&nbsp;&nbsp; MAX_ERRORS 500<br/>&nbsp;&nbsp; MERGE_MINIMUM 5<br/>&nbsp;&nbsp; NET_NAME_CHARS '#%&amp;()*+-./:=&gt;?@[]^_`|'<br/>&nbsp;&nbsp; NET_NAME_LENGTH 24<br/>&nbsp;&nbsp; OVERSIGHTS ON<br/>&nbsp;&nbsp; REPLACE_CHECK OFF<br/>&nbsp;&nbsp; SINGLE_NODE_NETS ON<br/>&nbsp;&nbsp; SPLIT_MINIMUM 0<br/>&nbsp;&nbsp; SUPPRESS&nbsp;&nbsp; 20<br/>&nbsp;&nbsp; WARNINGS ON</p><p>&nbsp;1 error detected<br/>&nbsp;No oversight detected<br/>&nbsp;No warning detected</p><p>cpu time&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 4:06:47<br/>elapsed time&nbsp; 0:02:27</p>
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