按照书中实例操作出错!!!
1、我安装的是Cadence SPB16.3,用Allegro PCB SI GXL打开Booksi_Demo_Allegro160_Unrouted.brd文件后出现如下警告:“database was last saved by a higher tier tool, allegro expert. there may be constraints,rules and other design data that may be ignored in this tool."这个问题应该怎么解决??
2、在对DDR1_A总线进行仿真的时候,出现错误:"Simulation aborted. part(s) with INVALID parameter values exist in the topology."这是怎么回事?应该怎么解决啊??
第二个问题解决了,把TL2和TL4的velocity参数添加上去就可以了
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