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CPLD的时钟??

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发表于 2007-6-14 17:52:00 | 显示全部楼层 |阅读模式
小弟我正在用CPLD开发控制方面的电路,但是看cpld的资料(英文)还是没有怎么看懂,想请问一下,像cypress 公司的cy37064p100-125ac的cpld它的工作频率是125M,它的频率怎么来的,是外界时钟输入还是它内部就存在这样一个电路产生这个时钟的?还有就是cpld本身它有四个时钟输入端口,但是看电路上面好像这四个时钟都没有用,怎么回事?这四个引脚用来干什么的?该芯片唯一的一个输入时钟是用于程序下载的JTAG口的TCLK(本人是看了合众达dsp c6000的电路图cpld后产生的疑问
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发表于 2007-6-15 15:02:00 | 显示全部楼层

应该 是外部给时钟吧。

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 楼主| 发表于 2007-6-15 18:07:00 | 显示全部楼层

先3q楼上的,你真是一个好人

但是它的时钟输入那是干什么的?是不是我们也可以通过这几个引脚来输入控制时钟(在I/O引脚不够时)?

英文如下:Clocking
Each I/O and buried macrocell has access to four synchronous
clocks (CLK0, CLK1, CLK2 and CLK3) as well as an
asynchronous product term clock PTCLK. Each input
macrocell has access to all four synchronous clocks.
Dedicated Inputs/Clocks
Five pins on each member of the Ultra37000 family are designated
as input-only. There are two types of dedicated inputs
on Ultra37000 devices: input pins and input/clock pins.
Figure 3 illustrates the architecture for input pins. Four input
options are available for the user: combinatorial, registered,
double-registered, or latched. If a registered or latched option
is selected, any one of the input clocks can be selected for
control.
Figure 4 illustrates the architecture for the input/clock pins.
Like the input pins, input/clock pins can be combinatorial,
registered, double-registered, or latched. In addition, these
pins feed the clocking structures throughout the device. The
clock path at the input has user-configurable polarity.
Product Term Clocking
In addition to the four synchronous clocks, the Ultra37000
family also has a product term clock for asynchronous
clocking. Each logic block has an independent product term
clock which is available to all 16 macrocells. Each product term
clock also supports user configurable polarity selection.

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 楼主| 发表于 2007-6-15 18:09:00 | 显示全部楼层
还问一个就是,它的工作频率达到125M,假如是外部给时钟的话,是不是就是外部最大的时钟输入是125M?
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发表于 2008-12-16 10:52:00 | 显示全部楼层

同问 LZ的问题

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