Allegro 导入 logic, 晕！

ice4521

我学过Protel99, Power PCB,都好学，现在学Allegro PCB Design 610,也就是现在的最新版Cadence 15.2.I am crazy .

好不容易装OK，初步试了下：[em06][em06][em06][em06][em06]。

1.在Design Entry CIS只用了两个电阻并联作的一个世界上最简单的电路图，导出netlist ,有三个*.dat的文件。

2.在Allegro PCB中做了一个板外框和放元件区，但是导入Logic时什么也没有。log文件如下：

Cadence Design Systems, Inc. netrev 15.2 Sat Feb 05 12:01:46 2005 (C) Copyright 2002 Cadence Design Systems, Inc.

------ Directives ------

RIPUP_ETCH FALSE; RIPUP_SYMBOLS NEVER; MISSING SYMBOL AS ERROR FALSE; SCHEMATIC_DIRECTORY 'F:\CADENCE V15.2\EX\allegro'; BOARD_DIRECTORY ''; OLD_BOARD_NAME 'start.brd'; NEW_BOARD_NAME 'start.brd';

CmdLine: netrev -$ -5 -i F:\CADENCE V15.2\EX\allegro -y 3 F:\CADENCE V15.2\EX\allegro\#Taaaaaa01600.tmp

------ Preparing to read pst files ------

Starting to read F:/CADENCE V15.2/EX/allegro/pstchip.dat Finished reading F:/CADENCE V15.2/EX/allegro/pstchip.dat (00:00:00.08) Starting to read F:/CADENCE V15.2/EX/allegro/pstxprt.dat Finished reading F:/CADENCE V15.2/EX/allegro/pstxprt.dat (00:00:00.00) Starting to read F:/CADENCE V15.2/EX/allegro/pstxnet.dat Finished reading F:/CADENCE V15.2/EX/allegro/pstxnet.dat (00:00:00.00)

------ Oversights/Warnings/Errors ------

------ Library Paths ------ MODULEPATH = . C:\Cadence\SPB_15.2\share\local\pcb/modules

PSMPATH = . symbols .. ../symbols C:\Cadence\SPB_15.2\share\local\pcb/symbols C:\Cadence\SPB_15.2\share\pcb/pcb_lib/symbols C:\Cadence\SPB_15.2\share\pcb/allegrolib/symbols

PADPATH = . symbols .. ../symbols C:\Cadence\SPB_15.2\share\local\pcb/padstacks C:\Cadence\SPB_15.2\share\pcb/pcb_lib/symbols C:\Cadence\SPB_15.2\share\pcb/allegrolib/symbols

------ Summary Statistics ------

netrev run on Feb 5 12:01:46 2005 DESIGN NAME : 'BILL' PACKAGING ON Apr 6 2004 19:58:38

COMPILE 'logic' CHECK_PIN_NAMES OFF CROSS_REFERENCE OFF FEEDBACK OFF INCREMENTAL OFF INTERFACE_TYPE PHYSICAL MAX_ERRORS 500 MERGE_MINIMUM 5 NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|' NET_NAME_LENGTH 24 OVERSIGHTS ON REPLACE_CHECK OFF SINGLE_NODE_NETS ON SPLIT_MINIMUM 0 SUPPRESS 20 WARNINGS ON

No error detected No oversight detected No warning detected

cpu time 0:04:10 elapsed time 0:00:01

hqgboy

hehe............

ice4521

以下是引用hqgboy在2005-2-5 14:16:51的发言： hehe............

有哪位大虾帮帮我，谢谢！

ice4521

我决定在此等-----全天在线-------直到[em06]----------------[em01]

lily_7948

你有没有按着教程的步骤？

ice4521

国内国外的教程一大堆，硬盘快爆了。

天天照着练，我的心快碎了。[em08]

lily_7948

上面的文件我也看不懂啊。我按着教程做，没有出现这个问题。只出现过封装不对或者找不到。

ice4521

谢谢帮我！对了。你用的是Cadence 15.2中的Allegro PCB Design 610吗？

netlists要找哪些文件才能导库？只有symbols行吗？

AK-74

你的网表和symbols的文件要放在一起吧！

ice4521

谁用过这个新生版本，大家多多指教。

不甚感激！！！！

给大家拜个早年！！！！