Signal Integrity Simulation of PCI Express Gen 2 Channel

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Overview
In the electronics industry, there has been an architectural shift over the past
several years from parallel bus interfaces to serial communication links. The benefits
of employing serial links over parallel I/O schemes include fewer device pins,
reduced board space requirements, smaller connectors, easier PCB layouts, and less
susceptibility to noise. However, there are unique challenges associated with serial
link design. The high data rate signals pose challenges previously only familiar to
analog RF and microwave designers. Today, many existing serial I/O standards operate
at multi-Gbps speeds. These standards are evolving, and the next generation
versions of the standards aim to increase (or perhaps even double) the data rates
achievable in a single lane. For example, PCI Express (PCIe) Gen 1 operates at 2.5
GT/s, while PCIe Gen 2 and PCIe Gen 3 are 5.0 GT/s and 8.0 GT/s, respectively. Further
complicating things is the fact that high-speed serial links often require special
data processing, such as SerDes (serializer/deserializer), equalization, and line coding
(i.e. 8B10B or 64B66B). For multi-Gbps serial links, a robust approach to signal
integrity simulation must be followed in order to avoid costly design iterations.
Figure 1 illustrates a typical link, which consists of driver and receiver ICs, their
packages, several connnectors, and PCBs. The passive components of the link are
collectively called the channel. To ensure signal integrity, it is crucial to carefully design
all aspects of these passive interconnects. At high data rates, it is critical that
the channel simulation accurately takes into account the distributed nature and loss
mechanisms of the transmission lines, coupling between the traces of differential
pairs and any adjacent aggressors/victims, and impedance mismatches. A good
practice is to create a virtual prototype of the entire link in a signal integrity EDA
(electronic design automation) tool and simulate the eye diagram performance.
To illustrate this design flow, a PCIe Gen 2 system, operating at 5 GT/s, is built and
simulated in Agilent’s high-frequency/high-speed EDA tool called ADS (Advanced
Design System).
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Signal Integrity Simulation of PCI Express Gen 2 Channel.pdf

pdayoyo

Many thanks for sharing.

leaiopewqs

非常感谢。。

hnbgerllz

Many thanks for sharing.