业界观察

winworm

Cadence Allegro 16.2将在第四季度发布，最引人注目的变化是支持IBIS-AMI，加速高速串行通道的仿真，下面是更新简介，Cadence China上有个中文的部分翻译稿（http://www.cadence.com.cn/fecn/press_detail.php?NID=300），纯粹是个外行翻译的，大家可以对比看看笑话：

eye masks      眼图掩模

New high frequency field solver     新的全波电磁场仿真器

bit error rate requirements         BER匹配性

The Cadence® Allegro® and Cadence OrCAD® family of products for PCB design and IC packaging/SiP design provide automation, advanced co-design, and constraint-driven flows that speed product development—from concept and capture to manufacturing. The latest Allegro and OrCAD release (16.2) enhances these solutions with new capabilities that address current and future business-driven technology challenges, including miniaturization, shorter product lifecycles, increasing design speeds, and environmental concerns.

  
 
Miniaturization/High-Density Interconnect
In the area of product miniaturization, significant improvements for designers using high-density interconnect (HDI) will be of particular value to customers in the high-end consumer and wireless handheld electronics market, as well as in the computing and networking segments where users are seeking a constraint-driven HDI design flow. "Cadence has excelled in constraint-driven PCB design flows for many years, but customers also increasingly demand an HDI capability," explains Steve Kamin, Group Director PCB and IC Packaging Product Marketing, Cadence Design Systems. "With the significant improvements in the latest release of our PCB and IC packaging technology, Cadence now offers both of these capabilities, and some of our customers already are seeing the benefits of our constraint-driven HDI design flow."

"Harris has worked closely with Cadence on improvements in Allegro," said Charlie Davies, Principal ECAE Application Engineer at Harris Government Communications Systems Division. "We are part of a small, diversified group of customers providing feedback to Cadence on improvements in Allegro 16.2. The biggest improvement in the Allegro 16.2 release has been in the area of designing PCBs using a build-up process with High-Density Interconnects. With the addition of capabilities for HDI, Allegro provides an excellent constraint-driven HDI design Flow. These advances along with other ease-of-use improvements will significantly improve our ability to execute our most difficult HDI design challenges, while reducing our design cycle time."
Enhancements such as these make 16.2 a very important release for PCB and IC package designers. For example, the HDI capability includes new features such as enhanced design rules for microvias and same-net elements, along with powerful automation-assisted interconnect and via pattern insertion. Manufacturing IP-driven wirebonding from Kulicke & Soffa and co-planar waveguide modeling further boost productivity and reduce manufacturing-driven ECOs.

Shrinking Product Lifecycles
To deal more effectively with product lifecycle issues, the Allegro and OrCAD 16.2 release delivers features such as extended rule-driven assembly rule checking for IC packages, auto-intelligent step and repeat of complex placement patterns, and enhanced automation for PCB layout-driven RF design. It also enables IC package/SiP team-based design to reduce design cycle time and make resource usage more efficient.

Additionally, all Allegro and OrCAD products—from front-end design creation to signal integrity to back-end layout—have been enhanced in the 16.2 release. One new capability enables customers to integrate RF circuits on PCBs together with digital and analog circuits. The Allegro PCB RF Option achieves this with two major enhancements: a bi-directional interface with the Agilent ADS RF design environment, and a new layout-driven RF design capability that makes it easier to modify RF circuits. The layout-driven RF design capability in the Allegro PCB RF Option also allows users to add RF circuit elements—stripline or microstrip elements—and the system will automatically create RF schematic elements through a back-annotation process. This eliminates the need for RF designers to manually create RF schematics for changes made in the layout, shortening design cycle times and reducing the risk of introducing manual errors.

The proven Cadence constraint-driven PCB design flow also provides additional control of constraints that electrical engineers need in specifying their design intent. Engineers can now specify physical and spacing constraints on critical nets and embed those in the design. These constraints are required for signals such as those found in DDRx memory interfaces, where the engineer needs to specify line widths and spacing to manage impedance and shield critical signals from crosstalk.

Cadence OrCAD Capture further delivers improved capabilities for designing FPGAs into products. Users can easily import an FPGA’s pin assignment from FPGA vendor tools. It also creates split symbols, and allows users to control how the symbols are split. This makes it easier to integrate an FPGA into the PCB design. Should a user choose to make changes to the FPGA pin assignment, OrCAD Capture provides the capability to export an updated pin assignment to the FPGA vendor’s tool. With this release, it supports Altera and Xilinx formats for import and export. Future support for other vendors will be provided based on customer requests.

Users of the 16.2 release will also notice improvements to the Graphical User Interface and Use Models in Allegro PCB Editor as well as other Allegro and OrCAD products. Enhancements include a new application mode for placement in Allegro and OrCAD PCB Editors, improved snapping capabilities with many choices on RMB, and new font support and keyboard shortcuts in Allegro Design Entry HDL.

Increasing Design Speeds/Streaming Data
As video data is being pervasively streamed throughout the Internet and wireless infrastructures, many products now require parallel memory interfaces (i.e. DDR3) running at speeds over a gigahertz and serial interfaces (i.e. PCI Express) transmitting 5 to 10 gigabits per second. The 16.2 release will help accelerate the development of these designs by enabling more accurate simulation and compliance testing of high frequency interfaces. Standard eye masks can now be easily incorporated into multi-bit simulations to insure that bit error rate requirements are met. New high frequency field solver technology is available to create S-parameter models for PCB structures and enhanced 3D field solver technology from preferred technology partner, Apache Design Solutions, can now be incorporated into the IC Package and SiP SI solutions to ensure accurate die to die modeling of high frequency interconnect. Modeling of advanced SerDes transceivers with the newly adopted IBIS-AMI standard now enables simulations with devices from different vendors at opposite ends of the serial link. This release includes a model development kit that can be used to develop IBIS 5.0 AMI compliant models. The new IBIS 5.0 standard is a result of Cadence, SerDes vendors, and other EDA companies coming together to enable accurate simulations of devices that are required for the latest serial link standards.

Environmental Concerns/Green Design
With the increasing awareness of the need to develop products that help protect the Earth’s climate and conserve resources, the 16.2 release helps companies go green. Design teams can make their products more efficient using new capabilities such as IC package power delivery analysis (which includes an integrated power analysis flow that is supported by 3D extraction of signal, power, and ground signals). It also includes the ability to optimize package PDN impedance voltage while minimizing voltage ripple. These and other enhancements also help co-design teams to optimize low-power system designs.

From improved high-speed flows to enhanced ease of use across the range of products, users will find a number of ways that the newest release of the Allegro and OrCAD family of products improves productivity and helps to address today’s and tomorrow’s critical challenges.

winworm

李老师最近很高产，即将出版3本SI/PI译作，质量如何，让我们拭目以待：

B.Young著, 李玉山等译，数字信号完整性：互连、封装的建模与仿真，机械电子工业出版社，2008(原版Prentice, 2001)

Mike P. Li著，李玉山等译，高速系统——抖动、噪声与信号完整性，电子工业出版社，2009(年内出版，原版Prentice, 2007)

M.Swaminathan, E. Enginet著，李玉山等译, 芯片及系统中的电源完整性建模与设计，电子工业出版社，2009(年内出版，原版Prentice, 2007 )

edwinzhu

winworm通晓的真多，服！

xiapi

[em01]

winworm

Synopsys发布Hspice例行更新，B-2008.9，与SI相关的更新主要是支持统计眼图分析，到此为止目前支持统计眼图分析的软件有：
Agilent ADS、Ansoft Nexxim、Sisoft QCD，Synopsys Hspice，即将发布的Cadence Allegro也会支持。


Signal Integrity
■ Statistical Eye Diagram Analysis: See the HSPICE User Guide: Simulation
and Analysis, Chapter 18, Statistical Eye Analysis.
■ TxLine Utility No license required: The W-element GUI utility, TxLine Tool,
can be used for creating transmission line models. TxTool is built into the
CosmosScope binary but HSPICE users do not need a CosmosScope
license key to run TxTool.
You can download the latest CosmosScope binary (or use any CosmosScope
binary you have previously downloaded) and run the TxLine tool. See the
section “Using the TxLine (Transmission Line) Tool Utility” in Chapter 3 of the
HSPICE User Guide: Signal Integrity.


Analysis of high-speed serial interfaces requires processing of millions of bits of
data making analysis by traditional analysis tools computationally expensive.
Eye diagrams are used extensively in the evaluation of high-speed serial
interfaces and as a fundamental performance metric for high-speed serial
interfaces in the bit error rate (BER). Statistical eye diagram techniques allow
eye diagrams and BER to be evaluated quickly and accurately.


Examples, Statistical Analysis Setup
Incident port definitions
p1 tx_in+ tx_in- 0 port=1
p2 in 0 port=2
Probe port definitions
p3 rxout+ rxout- 0 port=3
p4 out 0 port=4
Analysis statement
.stateye T = 400p trf=20p
+ incident_Port= 1, 2
+ probe_port = 3, 4
+ Rj = 5p, 5p, 2p, 2p tran_init = 50
+ T_resolution = 300 V_resolution = 300
Print, probe, and measure statements
.print stateye eye(4)
.print stateye ber(3)
.print stateye bathtubV(3, 0.9)
.print stateye bathtubT(4, 1n)
.probe stateye eye(4)
.probe stateye ber(3)
.probe stateye bathtubV(3, 0.9)
.probe stateye bathtubT(4, 1n)
.measure stateye eyevert Veye 4 time=1n tol=0.1n
.measure stateye eyehorz Heye 4 volt=0.9 tol=0.05
.measure stateye badbithigh WorstBits 3 time=1n state=high

winworm

令人期待的Mentor Hyperlynx V8.0，估计会在明年上半年推出，从V7到V8是质的变化，Mentor让我们等待太久：

电源完整性仿真，包括S参数模型拟合、转换，FDTD时域仿真、BEM频域仿真、DC Drop仿真
快速眼图仿真
CES与LineSim、BoardSim间的接口
信号旁路分析、DDR/DDR2/DDR3分析
平面噪声、DC压降的3D显示

mars

感谢 Winworm 为我们做的贡献，让我们学到了很多。

这两年没怎么关注SI，很多东西赶不上了，好好学习。

我的工具都是05年前的，赶不上时代了，呵呵...

winworm

Sigrity要跟Ansoft打官司：


SUNY, Sigrity File Patent Infringement Suit

SANTA CLARA, CA – Sigrity Inc. and The
Research Foundation of the State
University of New York (SUNY) have
filed a lawsuit against Ansoft Corp.
and ANSYS, Inc. for infringement
of U.S. Patent No. 5,504,423 titled
“Method for Modeling Interactions
in Multilayered Electronic Packaging
Structures.” The Research Foundation
is the owner and Sigrity is the exclusive
licensee of this patent.
The suit was filed on July 21, 2008
against Ansoft and alleges that Ansoft’s
products, including its SIwave product,
infringe the patent. An amended complaint
adding ANSYS as a defendant
was filed on August 5, 2008 as a result
of ANSYS’s acquisition of Ansoft,
which was effective July 31, 2008.

jeanny

原来大牛认为Allegro 16.2最引人注目的变化是支持IBIS-AMI,看来最近这个很热呀。

[此贴子已经被作者于2008-10-6 22:10:06编辑过]

winworm

EPEP(Electrical Performance of Electronic Packaging)是由IEEE Microwave Theory and Techniques Society、The IEEE Components, Packaging and Manufacturing Technology Society联合主办的研讨会，一年一次，今年是17届，主要针对当前高性能系统设计、高级封装设计，很多内容是SI、PI相关，从下面的日程表中可以看出业界当前研究的热点，另外一个很好的研讨会是由IEC主办的DesignCon，EPEP高校参与的多一些，偏理论，DesignCon公司参与多，偏工程。



Program for 2008

 Sunday, October 26, 2008

 

Mezzanine

12:00 -5:00 pm                           Registration for FDIP and EPEP Conference

 

California Ballroom H-J                       

1:15 – 5:55 pm                 FDIP Workshop

 
 
MONDAY, OCTOBER 27, 2008

 
Mezzanine

7:00 - 8:00 am                           Registration

 
Mezzanine

7:00 - 8:00 am                          Continental Breakfast

 
California Ballroom H-M
8:00 - 8:10 am                           Welcome/Introductory Remarks
                                                    Michael Lamson

 

8:10-8:40                                     Session I – Plenary/Keynote

                                               KEYNOTE: Ted Vucurevich

                                                                     Cadence Design Systems

                                             

8:40 – 10:00 am                           Session II – Power Integrity I

                                                     Session Chairs:

                                                     Brian Young , Texas Instruments

                                                     Tawfik Rehal-Arabi, Intel

                                                

Architecture Constraints over Dynamic Current Consumption

     Gilad Yahalom, Omer Vikinski and Gregory Sizikov............................................ Intel Corp

 

Verification and Co-Design of the Package and Die Power Delivery System Using Wavelets

     Imad A. Ferzli.................................................................................... University of Toronto

     Eli Chiprout......................................................................................................... Intel Corp

     Farid N. Najm................................................................................... University of Toronto

 

3D Power Distribution Network Co-design for Nanoscale Stacked Silicon IC

     Amirali Shayan, Xiang Hu, He Peng, Wanping Zhang and

       Chung-Kuan Cheng....................................................... University of California San Diego

     Mikhail Popovich and Xiaoming Chen................................................................ Qualcomm

 

Designs of Signal-Ground Bump-Patterns for Minimizing the Simultaneous Switching Noise in a Ball Grid Array

     Ruey-Bo Sun............................................................................. National Taiwan University

     Chien-Min Lin......................................................................................................... TSMC

     Ruey-Beei Wu........................................................................... National Taiwan University

 
San Jose Ballroom

10:00 – 10:15 am                         Refreshment Break

 

California Ballroom H-M            Tutorial I  

                                                      Session Chair:

                                                      Ram Achar, Carleton University

 

An End-to-End Multi-GHz Serial Channel Design Process

     Douglas B. White, Chong Ding, Stephen A. Scearce, Divya Gopinath and

     Robert J. Evans............................................................................................ Cisco Systems

                                                     

10:15 – 11:00 am                        

 

11:00 – 12:40                               Session III – High Speed Link

                                                     Session Chairs:

                                                     Moises Cases, IBM

                                                     Robert Evans, Cisco Systems

 

Design and Analysis of a TB/sec Memory System

     Wendemagegnehu T. Beyene, Chris Madden, Namhoon Kim, Hae-Chang Lee

     Rich Perego, Dave Secker, Chuck Yuan, Arun Vaidyanath and Ken Chang............ Rambus

 

Statistical Link Analysis of High-Speed Memory I/O Interfaces during Simultaneous Switching Events

Jihong Ren, Dan Oh, Sam Chang and Frank Lambrecht ......................................... Rambus

 

Pseudo-Differential Signaling Scheme Based on 4b/6b Multiwire Code

     Dan Oh, Fred Ware, WooPoung Kim, Joong-Ho Kim, John Wilson, Lei Luo,

     Jade Kizer, Ralf Schmitt, Chuck Yuan and John Eble...............................................Rambus

 

On-Chip Bus Signaling Using Passive Compensation

     Yulei Zhang and Ling Zhang............................................ University of California, San Diego

     Alina Deutsch, George Katopis and Daniel Dreps........................................................ IBM

     James Buckwalter.......................................................... University of California, San Diego

     Ernest Kuh....................................................................... University of California, Berkeley

     Chung-Kuan Cheng........................................................ University of California, San Diego

 

An Active Crosstalk Reduction Technique for Parallel High-Speed links in Low Cost Wirebond BGA Packages

     Yan Hu, Jikai Chen.............................................................................. University of Florida

     Michael Lamson......................................................................... Texas Instruments (retired)

     Rizwan Bashirullah............................................................................... University of Florida

 

California Ballroom C-G

12:40 – 1:40                                  Lunch (for conference attendees)

 

California Ballroom H-M

1:40 – 3:20                                    Session IV – Signal Integrity I

                                                      Session Chairs:

                                                      Dale Becker, IBM

                                                      Dan Oh, Rambus

 

SSN Mitigation By Means of a 2D EBG Structure with Square Patches and  

Meander Lines

     A. Ciccomancini Scogna............................................................................ CST of America

 

Compact Expressions for Period Jitter of Global Binary Clock Trees

     Jinwook Jang............................................................................ University of Massachusetts

     Olivier Franza........................................................................................... Intel Corporation

     Wayne Burleson....................................................................... University of Massachusetts

 

Multimode Signaling on Non-Ideal Channels

     Yongjin Choi, Chanyoun Won and Paul D. Franzon............. North Carolina State University

     Henning Braunisch and Kemal Aygün........................................................ Intel Corporation

 

CMOS Circuit Simulation Using Latency Insertion Method

     Tadatoshi Sekine and Hideki Asai......................................................... Shizuoka University

 

Chip-Package Co-Design Methodology for Global Co-Simulation of Re-Distribution Layers (RDL)

     Sidina Wane.................................................................................. NXP-Semiconductors 2

     An-Yu Kuo.................................................................................. Apache Design Solutions
 

San Jose Ballroom

3:20 -3:35 pm                         Refreshment Break

 

California Ballroom H-M

3:35 – 4:55 pm                        Session V – Measurement

                                                Session Chairs:

                                                Kathleen Melde, University of Arizona

                                                Ramesh Abhari, McGill University

 

On-chip Oscilloscope for Signal Integrity Characterization of Interconnects in

130nm CMOS Technology

     Pavle Milosevic and José E. Schutt-Ainé................. University of Illinois Urbana-Champaign

 

Measurement Techniques for On-chip Power Supply Noise Waveforms based on Fluctuated Sampling Delays in Inverter Chain Circuits

     Yutaka Uematsu, Hideki Osaka,  Eiichi Suzuki, Masayoshi Yagyu and

     Tatsuya Saito........................................................................................................... Hitachi

 

Correlation of PDN Impedance with Jitter and Voltage Margin for High Speed Channels

     Vishal Laddha and Madhavan Swaminathan......................... Georgia Institute of Technology

 

Accurate Resistance, Inductance, Capacitance, and Conductance (RLCG) from Uniform Transmission Line Measurements

     M. J. Degerstrom, B. K. Gilbert and E. S. Daniel................................................................

     .............................................. Mayo Clinic Special Purpose Processor Development Group

 

San Jose Ballroom

 

4:55– 6:30 pm                       Session VI - Open Forum (Posters)

                                              

 Design, Modeling, and Characterization of Embedded Electromagnetic Band Gap (EBG) Structure

     Suzanne Huh and Madhavan Swaminathan........................... Georgia Institute of Technology

     Fidel Muradali................................................................................ National Semiconductor

 

Simulation of Worst Case Switching Noise on a DDR2 Interface

     Rohan Mandrekar, Paul M Harvey, Jim Kuruts, Daniel Dreps, Tolga Ozguner,

     Yaping Zhou, Kazushige Kawasaki, Gary Lafontant and Gen Yamada......................... IBM

 

Placement of Shorting Vias for Power Integrity in Multi-Layered Structures

     Ssu-Hsuan Hsu, Yung-Shou Cheng and Wei-Da Guo................. National Taiwan University

     Hung-Hsiang Cheng and Chen-Chao Wang............... Advanced Semiconductor Engineering

     Ruey-Beei Wu........................................................................... National Taiwan University

 

Efficient Analysis for Multilayer Power-Ground Planes with Multiple Vias and Signal Traces in an Advanced Electronic Package

     Zaw Oo Zaw, Xing Chang Wei, En-Xiao Liu and Er-Ping Li

     ............................................................. A*STAR Institute of High Performance Computing           

     Le-Wei Li......................................................................... National University of Singapore

 

Analysis of Entire Power Distribution System of Chip, Package and

Board for High Speed IO Design

     Hsing-Chou Hsu........................................................................... Azurewave Technologies

     Jack Lin.................................................................................................................... Sigrity

 

Discussing Impedance Distribution with Multiple Stimulating Sources in

Power Distribution System Design and Simulation

     Zhen Mu...................................................................................... Cadence Design Systems

 

A Resonance-Free Power Delivery System Design Methodology Applying 3D Optimized Extended Adaptive Voltage Positioning

     Tao Xu and Brad Brim.............................................................................................. Sigrity

 

Analysis of EBG Structures using SPICE Models of Multiple Planes

     Naoki Kobayashi, Ken Morishita and Takashi Harada........................................................

     ...................................................................................... NEC System Jisso Research Labs

 

Multi-GHZ Modeling and Characterization of On-Chip Power Delivery Network

     Vishram S. Pandit and Woong Hwan Ryu................................................. Intel Corporation

 

Accurate Parasitic Inductance Determination of a Ceramic Capacitor through

2-Port Measurements

     Koh Yamanaga ..................... Tokyo Institute of Technology and Murata Manufacturing Co

     Takashi Sato and Kazuya Masu............................................. Tokyo Institute of Technology

 

Correlation of On-Die Capacitance for Power Delivery Network

     Yi-Feng Liu, Brian Wang, Mingming Xu, , Xiaoping Liu, Jie Zhu Chen and

     Michael Desmith.......................................................................................................... Intel

 

Hierarchical and Adaptive Finite-Element Reduction-Recovery Method for Large-Scale Power and Signal Integrity Analysis of High-Speed IC and Packaging Structures

     Houle Gan, Qing He and Dan Jiao............................................................ Purdue University

 

A Novel Stopband-Enhanced EBG Planes Using an Embedded Slow-wave Structure in Low-cost RF-SiP

     Chia-Yuan Hsieh, Hao-Hsiang Chuang and Ting-Kuang Wang

     ................................................................................................. National Taiwan University

     Chen-Chao Wang, Hung-Hsiang Cheng, Yei-Shen Wu, Chi-Tsung Chiu and

     Chih-Pin Hung.......................................................... Advanced Semiconductor Engineering

     Tzong-Lin Wu........................................................................... National Taiwan University

 

Ultra Wideband Wireless Serial Data Communication at 10Gb/s in CMOS 90nm

     Sameera Siddiqui and Tad Kwasniewski................................................... Carleton University

 

Effective Resolution of Design Issues in Telecommunication Blade Systems

     Bhyrav Mutnury, Nam Pham and Moises Cases........................................................... IBM

     Daniel N. De Araujo................................................................................................. Ansoft

 

A Dual-Slope Signaling Scheme to Suppress Electromagnetic Interference (EMI) with Sustaining Eye Margin

     Changwook Yoon................................................................................................... KAIST

     Seungyong Baek, HyungRok Lee and Youchul Jeong...................................... Silicon Image

     Jongbae Park and Hyunjeong Park.......................................................................... KAIST

     Baegin Sung................................................................................................... Silicon Image

     Joungho Kim........................................................................................................... KAIST

 

Characterization of Halogen-Free Package Materials Using Cavity Resonators

     Kemal Aygun and Grace Hu......................................................................................... Intel

 

Development of a Cost-Reduced Package thru DOE Validation and Zero-Margin Design Concept

     Jackson Kong, Jimmy Huang, Wan Ching Quah and Teong Keat Beh........................... Intel

 

Forwarded Clock based Receiver Characterization Methodology for Statistical Full Link Analysis Tools

  Santanu Chaudhuri, Rick L. Booth, Jayson Strayer, Nasser Kurd and

     Michael Sandhinti......................................................................................................... Intel

 

Analysis of Noise Coupling from Printed Circuit Board to Shielding Enclosure

     Zhenwei Yu................................................. Missouri University of Science and Technology

     Xiaopeng Dong, Jason Mix and Kevin Slattery............................................................. Intel

     Jun Fan........................................................ Missouri University of Science and Technology

 

California Ballroom D

7:30 -9:00 pm                 TPC Committee Meeting/Dinner

 

TUESDAY, OCTOBER 28, 2008

 

Mezzanine

7:00 - 8:00 am                             Continental Breakfast
 
California Ballroom H-M

8:00 – 8:45 am                             Tutorial II

                                                      Session Chair:

                                                      Ram Achar, Carleton University

 

Power Integrity for I/O Interfaces

   Vishram S. Pandit, Myoung J. Choi and Woong Hwan Ryu......................... Intel Corporation

                                                     

California Ballroom H-M

8:45-10:25                                Session VII – Power Integrity II

                                                   Session Chairs:

                                                   Christopher Pan, Qualcomm

                                                   Greg Taylor, Intel

 

Effectiveness of On-Die Decoupling Capacitance in Improving Chip Performance

     Isaac Kantorovich and Chris Houghton......................................................................... Intel

 

An Adaptive On-chip ESR Controller Scheme in Power Distribution Network for Simultaneous Switching Noise Reduction

     Jongjoo Shim and Minchul Shin............................................................................... KAIST

     Hyungsoo Kim, Yongju Kim and Kunwoo Park.............................. HYNIX Semiconductor

     Jeonghyeon Cho and Joungho Kim ......................................................................... KAIST

 

Suppression of Vertical Coupling using Electromagnetic Band Gap Structures

     Nithya Sankaran, Suzanne Huh, Madhavan Swaminathan and Rao Tummala........................

     ........................................................................................... Georgia Institute of Technology

 

Including the Impact of Connecting Vias in the Performance Metric Evaluation for Board-Level Optimization of Decoupling Capacitors

     Mosin Mondal.............................................................................. University of Washington

     Samuel Connor and Bruce Archambeault..................................................................... IBM

     Vikram Jandhyala......................................................................... University of Washington

 

Robust Iterative Finite Element Solver for Multi-terminal Power

Distribution Network Resistance Extraction

     Martien Oppeneer........................................................ Eindhoven University of Technology

     Prasad Sumant and Andreas C. Cangellaris............. University of Illinois Urbana-Champaign

 
San Jose Ballroom

10:25 - 10:40  am                  Refreshment Break

 

California Ballroom H-M

10:40 – 12:20                           Session VIII - Macromodels

                                                 Session Chairs:                   

                                                 Flavio Canavero, Politecnico di Torino

                                                 Dhamendra Saraswat

 

The Design of Continuous-Time Linear Equalizers Using Model Order Reduction Techniques

     Wendemagegnehu (Wendem) T. Beyene................................................................ Rambus

 

Parallel Algorithm for Analysis of High-Speed Interconnects

     D. Paul, N. M. Nakhla, R. Achar and M. S. Nakhla............................. Carleton University

 

Nonlinear Circuit Solver with Linear Interconnect Load

     Albert E. Ruehli and Jerry Hayes................................................................................ IBM

 

Compact Macromodeling of Electrically Long Interconnects

     A. Chinea, P. Triverio, and S. Grivet-Talocia....................................... Politecnico di Torino

 

Passivity Enforcement via Quadratic Programming for Element-by-Element

Rational Function Approximation of Passive Network Matrices

     Se-Jung Moon and A.C. Cangellaris................... University of Illinois at Urbana-Champaign

 
California Ballroom C-G

12:20 am - 1:45 pm                    Lunch (for Meeting attendees)

 

Monterey Room

12:20 - 1:45                                 Technical Program Committee Meeting

                                                     (Committee Members only)
California Ballroom H-M

1:45 – 2:30 pm                           Special Session - SI Education

                                                   Session Chair:

                                                   Ram Achar, Carleton University

 

An Industry-Oriented Curriculum in the Design and Performance of Electrical Packaging and Interconnect

     Robert J. Evans and Stephen Scearce........................................................... Cisco Systems

     Minjhing Hsieh.................................................................................... Engineering Learning

 

San Jose Ballroom

2:30 – 3:00 pm                             Refreshment Break

 

California Ballroom H-M

3:00 – 4:20 pm                             Session IX – Signal Integrity II

                                                     Session Chairs:

                                                     Chuck Yuan, Tambus

                                                      Stefano Grivet-Talocia, Politecnico di Torino
 

Sensitivity Computation of Interconnect Capacitances with respect to

Geometric Parameters

     Yu Bi and K. van der Kolk................................................... Delft University of Technology

     D. Ioan......................................................................... Politechnica University of Bucharest

     N.P. van der Meijs............................................................... Delft University of Technology

 

An Analysis on Measurement Sensitivity of Short-Pulse Propagation Technique Using a Virtual Test Bench

     Zhen Zhou.......................................................................................... University of Arizona

     Alina Deutsch.............................................................................................................. IBM

     Kathleen L. Melde.............................................................................. University of Arizona

     George A. Katopis and Jason D. Morsey.................................................................... IBM

 

An Efficient Inductance Extraction Algorithm for 3-D Interconnects with

Frequency Dependent Nonlinear Magnetic Materials

     Yang Yi, Vivek Sarin and Weiping Shi............................................. Texas A&M University

 

High Frequency Loss Characterization of FCPBGA Package Materials with Humidity and Temperature Variation

     Jean Audet and Nanju Na........................................................................................... IBM
 
San Jose Ballroom                       Session X – Open Forum (Posters)

4:20 – 6:20 pm                            

 

A Simple Method of Generating Causal Broadband RLGC Models

for CPW Transmission Lines with Surface Roughness

     Zhen Zhou and Kathleen L. Melde...................................................... University of Arizona

 

Fast Iterative Solution Algorithms for the Frequency-Domain Layered Finite-Element Based Analysis of Large-Scale On-Chip Interconnect Structures

     Feng Sheng and Dan Jiao......................................................................... Purdue University

 

Compact On-Chip Wire Models for the Clock Distribution of High-Speed I/O

Interfaces

     Xiaoning Qi, Joong-Ho Kim, Ling Yang, Ralf Schmitt and Chuck Yuan................... Rambus

 

Parallel Full-Chip Transient Simulation at Transistor Level

     He Peng and Chung-Kuan Cheng................................... University of California, San Diego

      Khosro Rouz and Manjit Borah................................................................ Fastrack Design

 

Design-performance aspects of Glass Ceramic in comparison to Alumina Ceramic and Organic FCPBGA Packages for High Link Densities of High Speed SerDes

     Haitian Hu, Nanju Na, Franklin Baez and Gary Lafontant............................................. IBM

 

Eliminating Via-Plane Coupling Using Ground Vias for High-Speed Signal Transitions

     Songping Wu and Xin Chang....................... Missouri University of Science and Technology

     Christian Schuster............................................................ Hamburg Univerity of Technology

     Xiaoxiong Gu.............................................................................................................. IBM

     Jun Fan........................................................ Missouri University of Science and Technology

 

Transient Simulation of Lossy Interconnects using the Latency Insertion Method (LIM)

     Dmitri Klokotov and José Schutt-Ainé................ University of Illinois at Urbana-Champaign

 

Effects of Partially Broken HF Signal Return on Different Packaging Levels

     Thomas-Michael Winkel and Roland Frech.........................................................................

     ....................................................................... IBM Deutschland Research & Development

     Thomas Gneiting................................................................................................... AdMOS

 

On Addressing the Practical Issues in the Extraction of RLGC Parameters for

Lossy Multiconductor Transmission Lines using S-parameter Models

     Madhusudanan K Sampath.......................................................... Advanced Micro Devices

 

Utilizing Low Loss Dielectric Material for High Performance DRAM

Window-BGA Design

     Hung-Hsiang Cheng, Chih-Yi Huang, Chen-Chao Wang, Chi-Tsung Chiu and

     Chih-Pin Hung.......................................................... Advanced Semiconductor Engineering

 

Controlled Impedance Chip-to-Chip Interconnect Using Coplanar Wire Bond Structures

     Samuel Harkness, Jeffrey Meirhofer and Brock J. LaMeres.......... Montana State University

 

A Parameterized Model Order Reduction Technique for Efficient Solution of FEM Eigenvalue Problems

     Majid Ahmadloo and Anestis Dounavis.................................. University of Western Ontario

 

Fast Reduced-Order Finite-Element Modeling of Lossy Coupled Wires Using Lumped Impedance Elements

     Shih-Hao Lee and Jian-Ming Jin......................... University of Illinois at Urbana-Champaign

 

Thermal Modeling of On-Chip Interconnects and 3D Packaging Using EM Tools

     Lijun Jiang   ................................................................................................................ IBM

     Seshadri Kolluri........................................................ University of California, Santa Barbara

     Barry J. Rubin, Howard Smith, Evan G. Colgan, Michael R. Scheuermann,

     Jamil A. Wakil, Alina Deutsch and Jason Gill................................................................ IBM

 

An H2-Matrix-Based Integral-Equation Solver of Linear-Complexity for

Large-Scale Full-Wave Modeling of 3D Circuits

     Wenwen Chai and Dan Jiao..................................................................... Purdue University

 

Time-Domain Orthogonal Finite-Element Reduction-Recovery (OrFE-RR) Method for Fast and Accurate Broadband Simulation of Die-Package Interaction

     Duo Chen and Dan Jiao.......................................................................... Purdue University

 

Proximity Interconnect Technology Utilizing Transmission Line Coupling for Stacked VLSI Chips

     Daisuke Iguchi............................................................................................. Fuji Xerox Co.

     Yutaka Akiyama....................................................................................... Meisei University

     Tsuneo Ito............................................................................................... Excel Service Co.

     Kanji Otsuka............................................................................................ Meisei University

 

AC Coupled Backplane Communication Using Embedded Capacitor

     Bruce Su............................................................................. North Carolina State University

     Pravin Patel, Steve W. Hunter and Moises Cases......................................................... IBM

     Paul D. Franzon.................................................................. North Carolina State University

 

Computer Code for Fast Macromodeling of Large Multiport Systems

     Dirk Deschrijver........................................................................................ Ghent University

     Bjorn Gustavsen ........................................................................ SINTEF Energy Research

     Tom Dhaene.............................................................................................. Ghent University

 

An Over-12-Gbps On-Chip Transmission Line Interconnect with a Pre-Emphasis Technique in 90 nm CMOS

     Kazuya Miyashita, Takahiro Ishii, Hiroyuki Ito, Noboru Ishihara and

     Kazuya Masu........................................................................ Tokyo Institute of Technology

 

Signal Integrity Improvement in Transmission Lines Backed by an EBG Structure

     Jin Chen and Ramesh Abhari.................................................................... McGill University

 

 
WEDNESDAY, OCTOBER 29, 2008

 
Mezzanine

7:00 - 8:00 am                       Continental Breakfast

 
California Ballroom H-M

8:00 – 9:20 am                       Session XII – Signal Integrity III\

                                               Session Chairs:

                                                        Vikram Jandhyal, Washington State University

                                               Ruey-Beei Wu, National Taiwan University

                                             

Minimizing Crosstalk Noise in Vias or Pins by Optimizing Signal Assignment in a High-Speed Differential Bus

     Yaping Zhou, Rohan Mandrekar, Tingdong Zhou, Sungjun Chun, Paul Harvey

     and Roger Weekly...................................................................................................... IBM

 

Impedance Design for Multi-layered Vias

     Xiaoxiong Gu, Albert E. Ruehli and Mark B. Ritter...................................................... IBM

 

Fewest Vias Design for Microstrip Guard Trace by Using Overlying Dielectric

    Yung-Shou Cheng and Wei-Da Guo........................................... National Taiwan University

     Guang-Hwa Shiue............................................................. Chung Yuan Christian University

     Hung-Hsiang Cheng and Chen-Chao Wang............... Advanced Semiconductor Engineering

     Ruey-Beei Wu........................................................................... National Taiwan University

 
Suppression of Power/Ground Noise Using Differential Vias

     Ruiming Chen, Haining Wang and Ramesh Abhari..................................... McGill University

 

9:20 – 10:05 am                   Tutorial III

                                              Session Chair:

                                              Ram Achar, Carleton University

 

Enhancing the Efficiency of Computer-Aided Analysis for Signal Integrity                                               through Model Complexity Reduction                      

     Andreas Cangellaris............................................... University of Illinois, Urbana-Champaign

 

Mezzanine

10:05 – 10:20 am                   Refreshment Break

 

California Ballroom H-M

10:20-12:05                            Session XIII– EM Modeling

                                                 Session Chairs:

                                                 Albert Ruehli, IBM

                                                 Daniel de Araujo, Ansoft

 

Multi-Layer Fringe-Field Augmentations for the Efficient Modeling of Package Power Planes

     Krishna Bharath, Nithya Sankaran, A. Ege Engin and Madhavan Swaminathan....................

     ........................................................................................... Georgia Institute of Technology

 

Accuracy-Preserving Adaptive Sampling of Broadband Electromagnetic

Spectra of Interconnect Structures

     Joon Hyung Chung and Andreas C. Cangellaris...................................................................

      ......................................................................... University of Illinois at Urbana-Champaign

 

Chip-Package Co-Simulation with Multiscale Structures

     Myunghyun Ha, Krishna Srinivasan and Madhavan Swaminathan.........................................

     ........................................................................................... Georgia Institute of Technology

 

A Methodology for Incorporating Metallization Loss in the

Electromagnetic Modeling of the Power Distribution Network

     Varvara Kollia and Andreas C. Cangellaris.........................................................................

     .......................................................................... University of Illinois at Urbana-Champaign

 

Packaging Modeling Using Fast Broadband Surface Integral Equation Method

     Zhi Guo Qian and Weng Cho Chew.................... University of Illinois at Urbana-Champaign

 

California Ballroom D-G

12:05 – 1:00 pm                    Lunch (for Meeting attendees)

                                              Awards

                                              Closing Remarks