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nwu

可否请版主谈谈高速连接器 这个领域 在SI比较少谈到

winworm

高速系统设计--抖动、噪声和信号完整性

【原 书 名】  Jitter, Noise, and Signal Integrity at High-Speed
【原出版社】 Prentice Hall PTR
【作　　者】(美)李鹏(Mike Peng Li) [同作者作品]
【译　　者】 李玉山;潘健[同译者作品]
【丛 书 名】 国外电子与通信教材系列
【出 版 社】 电子工业出版社     【书 号】 9787121089060
【上架时间】 2009-7-17
【出版日期】 2009 年7月 【开 本】 16开 【页 码】 228     【版 次】1-1


摩尔定律依然指引着世界半导体产业的技术路线图。目前，集成电路(IC)的特征尺寸已经降到65 nm，近期还将进一步做到45 nm、32 nm，甚至 22 nm等。它将使得IC系统具有更多的功能及更强的数据处理能力。显然，一个高效的复杂多功能系统需要快速的输入输出(I/O)能力。所以，当先进的 IC系统中晶体管数目不断增加时，I/O的速度也在不断地升高。
尽管特征尺寸的降低及I/O速度的升高赋予系统更好的功能和性能，它们同时也带来了技术上的挑战。I/O速度的升高使得链路总的可用最大抖动预算——单元区间(UI)必将相应地减小。为了确保整个链路系统能有较好的误码率(BER)，此时最严峻的挑战就是要降低抖动。特征尺寸减小带来另一个非常严峻的挑战是功率密度和功率损耗必须小于某一约束的限度，或者说要采用低功耗设计。这时，必须降低噪声以便在低功耗/低电压信号时能保持一个合理的信号噪声比(SNR)，从而噪声指标又变成了一个很关键的因素。当信道材料不变时，在同样有损信道条件下随着数据速率的升高，高频分量将迅速增加，这时的数据信号衰减和退化将加剧。信号的衰减和退化造成的信号完整性(SI)问题主要表现为确定性抖动及噪声。出于成本效益的考量，一般采用常规信道材料及多种高速I/O标准的技术途径去提高I/O链路的数据速率，这时对抖动、噪声及SI的挑战将会更加严峻。
今天，面向计算机的应用主要以铜线作为信道，其高速I/O速率标准大都设计为5～6 Gb/s，其中包括：PCI Express Ⅱ (5 Gb/s)，Serial ATA Ⅲ(6 Gb/s)以及FB DIMM Ⅰ(3.2,4.0,4.8 Gb/s)等。这些标准的下一代数据速率可能会提高到8～12 Gb/s。另一方面，面向网络的一些应用主要以光纤作为信道，大多数速率都设计为8～10 Gb/s，例如 Fibre Channel 8X(8.5 Gb/s)，Gigabit Ethernet(GBE)10X(10 Gb/s)以及 SONET OC?192(10 Gb/s)等。这些网络I/O链路的下一代数据速率可能会加倍或翻两番到17～40 Gb/s。在10 Gb/s 时，UI为100 ps；而40 Gb/s时，UI仅为25 ps。为了维持一个好的BER(例如10-12)，这类数据率下I/O链路中的随机抖动必须在亚皮秒(ps)甚至更低，这是一项十分严峻又具挑战性的任务。可以想象，将来随着数据率进一步的提高，抖动、噪声和SI带来的挑战将会变得更加严重。
20多年来，出版了许多信号完整性的书籍。但是书中涉及抖动、噪声和BER的部分都相当简短。只有两本书比较详细地论述过抖动，但由于它们已经过去了15～17年，与现在关于抖动、噪声及SI的知识及认知水平相比，那些内容也显得过时了。
过去10年中的巨大进展已经为抖动、噪声和信号完整性建立了新的理论和算法。关于抖动的定理及分析，抖动分量中的确定性抖动(DJ)、随机抖动(RJ)以及相关数学模型正在成为对抖动加以量化的更好度量。关于抖动跟踪，抖动传递函数已被广泛应用于定量求解抖动、噪声及信令的输出和冗余度分析。基于概率密度函数(PDF)、累积分布函数(CDF)以及相应卷积运算的统计信号分析方法正逐渐取代常规落后的、简单又不准确的峰-峰值和RMS等度量。正规地采用线性时不变(LTI)定理，加上统计信令及电路定理，可以求解链路系统及其子系统中的抖动、噪声和信令性能等。
与此同时，在高速网络和计算机I/O链路的体系结构和数据传输速度方面也取得了巨大的进展。总的来说，这些标准提出的体系结构都是以几个Gb/s的速率串行传输，在接收器采用时钟恢复电路 (CRC)提取时钟时序。CRC可以跟踪并降低接收器输入端的低频抖动以维持接收器及整个系统良好的BER性能。已经开发出许多时钟及数据恢复算法与电路，其中有些是基于锁相环(PLL)、相位内插(PI)及过采样(OS)的。每一种时钟恢复都给出了不同的抖动传递函数、跟踪能力及其特色。为了减轻或者补偿有损信道造成的信号退化影响，已经研究出多种先进的均衡技术及电路，包括线性均衡(LE)、判决反馈均衡(DFE)等。为了应对在新的数倍Gb/s高速I/O链路中出现的新体系结构、数据速率、时钟恢复及均衡等问题带来的挑战，已经研究出一些新的定理、算法、设计及测试技术。
过去10年，在对抖动、噪声及SI的理解、建模和分析方面，建立了全新的理论、算法和方法学。同时也研究出了用于减缓抖动、噪声及SI的链路结构、理论、算法和电路。然而，还没有一本系统论述并集中介绍抖动、噪声及SI最新进展的书籍。本书就是为了填补这方面的空白而撰写的。
本书试图以全面系统、深入易懂的方式对涉及时钟和I/O链路信令中抖动、噪声以及SI的基本原理、最新理论算法、建模、测试、分析方法加以评价和论述。本书涵盖的重点专题有：抖动和噪声的分离理论和算法；用于分析输出及冗余度的抖动传递函数；时钟及PLL抖动；对链路系统及其子系统(包括发送器、接收器、信道、参考时钟、PLL)抖动、噪声及SI等的建模、分析与测试技术。
在第1章中，首先概述在通信链路系统中有关抖动、噪声及SI的基础知识。接着，讨论各种抖动、噪声及SI的内在机理；介绍抖动和噪声的统计处理技术。然后，进一步讨论抖动和噪声分量的概念、定义及其必要性和重要性。最后，把对抖动、噪声及SI的讨论纳入到通信系统的框架之中。
有了第1章关于抖动、噪声、SI和链路通信系统的宏观描述，第2章深入地介绍必要的相关数学知识。这一章讨论了与抖动、噪声及SI相关的统计学和随机处理理论，线性系统和信令的线性时不变(LTI)理论以及将统计学与LTI相结合的理论等。
在第3，4章中，根据第2章中引入的统计学和随机理论，采用合适的PDF，CDF以及功率谱密度(PSD)，给出抖动、噪声、SI以及BER的量化指标。第 3章，我们用PDF和PSD、分量PDF与整体PDF的关系，以及分量PSD与整体PSD的关系来定量表征每个抖动和噪声分量。第4章，在一个二维 (2?D)的框架内联合讨论抖动和噪声。给出抖动和噪声联合的PDF(如眼图轮廓)，以及抖动和噪声联合的CDF(如BER轮廓)数学表征。
在第 5，6章中，研究将抖动和噪声分解为各个层次的分量。第5章采用普遍认同的尾部拟合法，基于抖动的PDF或CDF函数，将抖动分解成确定性抖动(DJ)和随机抖动(RJ)分量。第6章介绍基于抖动实时函数或自相关函数的分离技术，将其分离成第一层和第二层抖动分量，包括数据相关性抖动(DDJ)、占空失真 (DCD)、符号间干扰(ISI)、周期性抖动(PJ)、有界非相关抖动(BUJ)以及RJ等。介绍采用傅里叶变换(FT)的抖动谱或者PSD估计。这一章同时介绍了时域和频域的分离技术。
前面已经准备了足够的基础知识，包括统计抖动、噪声和SI；从分量的抖动或噪声PDF，PSD构建整体的 PDF，PSD；从抖动或噪声整体的PDF，PSD分离出分量的PDF，PSD理论和算法；下面就着手解决实际问题。高频时的时钟和PLL抖动是改善性能的主要障碍，我们将重点探讨时钟和PLL应用中的抖动问题。第7章专门研究时钟抖动。从时钟抖动的定义出发，揭示它对于同步和异步系统的影响。然后介绍三种不同的抖动类型：相位抖动、周期抖动和周期间抖动，以及其物理含义、模型和在时域和频域中的相互关系。最后，讨论了相位抖动与相位噪声的关系和映射数学模型，给出了一个微波/射频(RF)领域广泛使用的时钟和PLL性能的频域测度。第8章重点讨论PLL中的抖动和噪声。首先，介绍时域和频域用于PLL的 LTI模型以及定性和定量分析方法。其次，介绍采用时域互相关函数和频域PSD的一般抖动/噪声分析及建模技术。再次，给出2阶、3阶PLL中抖动、噪声和传递函数全面深入的建模分析方法。
第9，10，11章专门研究高速链路中的抖动、噪声及SI，包括三个重要的方面：物理机理；建模与仿真技术；测试与验证技术。为了真正理解抖动、噪声及SI，第9章专门研究其物理机理。第9章给出子系统，包括发送器、接收器、信道和参考时钟的体系结构，以及内部的抖动、噪声和SI物理机理。第10章研究高速链路系统及子系统的定量建模与分析。已经研究出根据LTI定理对子系统建模的方法，再用LTI的级联对整个系统建模。该章给出了子系统，包括发送器、接收器和信道等子系统的抖动、噪声和信令模型。均衡化和时钟恢复中的重要元素也体现在建模中，这里的均衡包括线性和DFE两种类型。第11章研究高速链路系统及子系统的测试与分析技术。该章给出链路子系统，包括发送器、接收器、信道、参考时钟和PLL的测试需求及方法。参考接收器由参考时钟恢复及均衡器组成，对该接收器抖动、噪声、信令输出的最新测试方法，以及用于测试该接收器冗余度的最坏情况抖动、噪声、信令产生方法也一并给出。在该章末尾，介绍了链路系统层次的测试方法，如环回(loopback)法等。此外，对片上自建内测试(BIST)与片外测试如何折中选择也进行了讨论。
第12章是全书的总结，探讨了抖动、噪声及SI的研究发展趋势、前景展望和面临的新挑战。
本书的主要读者对象是工业界高速电路、器件和系统领域的工程师和管理人员。不同方面的工程师，包括设计工程师、测试工程师、应用工程师和系统工程师，不管是已经涉足或者是将要涉足抖动、噪声、信号完整性和高速链路这一领域，都可以从阅读本书中受益。本书的另一类读者对象是在本领域或是将要进入本领域的研究人员、教授和学生。本书的宗旨是帮助读者对抖动、噪声、信号完整性和高速链路信令及性能，获得一个全面的理解。


第1章  绪论
1.1  抖动、噪声和通信系统基础
1.1.1  什么是抖动、噪声和信号完整性
1.1.2  抖动和噪声如何影响通信系统的性能
1.1.2.1  误码机理
1.1.2.2  误码率
1.2  时序抖动、幅度噪声和信号完整性的根源
1.2.1  固有噪声和抖动
1.2.1.1  热噪声
1.2.1.2  散弹噪声
1.2.1.3  闪烁噪声
1.2.2  噪声转化为时序抖动
1.2.3  非固有噪声和抖动
1.2.3.1  周期性噪声和抖动
1.2.3.2  占空失真(DCD)
1.2.3.3  符号间干扰(ISI)
1.2.3.4  串扰
1.3  抖动、噪声的统计信号描述
1.3.1  峰-峰值和均方根RMS描述
1.3.2  抖动或噪声的概率密度函数及分量描述
1.4  抖动、噪声和BER的系统描述
1.4.1  参考基准选取的重要性
1.4.2  串行数据通信中的抖动传递函数
1.5  抖动、噪声、BER和信号完整性研究述评
1.6  全书概要
第2章  抖动、噪声及信号完整性的统计信号与线性理论
A部分： 概率，统计量和随机信号
2.1  随机变量及其概率分布
2.1.1  随机变量和概率
2.1.1.1  基本定义
2.1.1.2  联合概率
2.1.1.3  条件概率
2.1.1.4  统计独立性
2.1.2  概率分布函数
2.1.2.1  概率密度函数(PDF)
2.1.2.2  累积分布函数(CDF)
2.1.2.3  PDF和CDF之间的关系
2.1.2.4  多个相关变量的PDF
2.1.2.5  多维随机变量的PDF和CDF
2.1.2.6  独立变量的PDF和CDF
2.1.2.7  两个随机变量之和的PDF
2.2  统计估计
2.2.1  数学期望或均值
2.2.2  方差
2.2.3  矩
2.2.3.1  二阶中心矩与方差
2.2.3.2  三阶中心矩及偏度
2.2.3.3  四阶中心矩及峰度
2.2.4  切比雪夫不等式
2.2.5  相关性
2.3  采样与估计
2.3.1  采样估计与收敛
2.3.1.1  均值、均方差和峰-峰值估计
2.3.1.2  大数定理
2.3.1.3  估计量的收敛性
2.3.2  中心极限定理
2.4  随机过程与谱分析
2.4.1  随机过程的PDF和CDF
2.4.2  随机过程的统计估计量
2.4.3  几种随机过程形式
2.4.3.1  广义平稳随机过程(WSS)
2.4.3.2  狭义平稳随机过程
2.4.3.3  各态历经随机过程
2.4.3.4  不同随机过程之间的关系
2.4.4  信号功率和功率谱密度(PSD)
2.4.4.1  PSD的定义
2.4.4.2  PSD和维纳-辛钦定理
B部分：线性系统理论
2.5  线性时不变系统
2.5.1  时域分析
2.5.2  频域分析
2.5.3  LTI系统的性质
2.5.3.1  交换律
2.5.3.2  分配律
2.5.3.3  结合律
2.5.3.4  级联性
2.6  LTI系统的统计估计量
2.6.1  均值
2.6.2  自相关函数
2.6.3  均方值
2.7  LTI系统的功率谱密度
2.7.1  输出的功率谱密度
2.7.2  输出自相关函数
2.8  小结
参考文献
第3章  抖动及噪声的根源、机理与数学模型
3.1  确定性抖动(DJ)
3.1.1  数据相关性抖动(DDJ)
3.1.1.1  基本理论
3.1.1.2  RC LTI系统的DDJ估计
3.1.1.3  仿真
3.1.1.4  占空失真
3.1.1.5  符号间干扰(ISI)
3.1.1.6  DDJ的通用模型
3.1.2  周期性抖动(PJ)
3.1.2.1  单PJ的PDF
3.1.2.2  单PJ的频谱
3.1.2.3  双PJ的PDF
3.1.2.4  双PJ的频谱
3.1.2.5  多PJ(N>2)的PDF
3.1.2.6  多PJ(N>2)的频谱
3.1.3  有界不相关抖动BUJ
3.1.3.1  BUJ的PDF
3.1.3.2  BUJ的频谱
3.2  随机抖动
3.2.1  高斯抖动
3.2.1.1  高斯分布的PDF
3.2.1.2  高斯抖动的PSD
3.2.2  高阶f-α抖动
3.2.2.1  f-α抖动的PDF
3.2.2.2  f-α的PSD
3.3  总抖动PDF与PSD
3.3.1  总抖动的PDF
3.3.2  总抖动的PSD
3.4  小结
第4章  抖动、噪声、误码率及相互关系
4.1  眼图和BER要点
4.2  总抖动PDF与各分量PDF的关系
4.2.1  总抖动的PDF
4.2.2  抖动PDF的卷积
4.2.3  眼图结构对应的抖动PDF
4.3  总噪声PDF与各分量PDF的关系
4.3.1  总幅度噪声的PDF
4.3.2  噪声PDF的卷积
4.3.3  眼图结构对应的噪声PDF
4.4  时序抖动和幅度噪声的联合PDF
4.4.1  通用二维PDF
4.4.2  二维高斯分布
4.5  BER与抖动/噪声的关系
4.5.1  时序抖动和BER
4.5.2  幅度噪声和BER
4.5.3  抖动和噪声共同作用下的BER
4.6  小结
第5章  统计域抖动及噪声的分离与分析
5.1  抖动分离的原因和目的
5.1.1  实际抖动分析及测试中的直接观测量
5.1.2  表征、诊断和调试中的需求
5.1.3  统计域中抖动分离方法概述
5.2  基于PDF的抖动分离
5.2.1  针对PDF的尾部拟合法
5.2.1.1  总抖动的PDF及其与DJ PDF和RJ PDF的关系
5.2.1.2  算法实现
5.2.1.3  蒙特卡罗仿真
5.2.2  通过反卷积确定DJ的PDF
5.2.2.1  反卷积原理
5.2.2.2  反卷积仿真
5.3  基于BER CDF的抖动分离
5.3.1  针对BER CDF的尾部拟合法
5.3.2  “变换的” BER CDF的尾部拟合法
5.3.3  从BER CDF或 Q因子中估计DJ PDF
5.3.4  从BER CDF中估计总抖动TJ
5.4  直接型双狄拉克抖动分离法
5.4.1  总抖动PDF
5.4.2  总BER CDF
5.4.3  直接型 “双δ” DJ模型的精度
5.4.3.1  对应DJ PDF变化范围的BER CDF误差
5.4.3.2  对应BER CDF值变化范围的DJ误差
5.5  小结
参考文献
第6章  时域、频域抖动及噪声分离与分析
6.1  抖动的时域及频域表征
6.1.1  抖动的时域表示
6.1.2  抖动的频域表示
6.1.2.1  直接傅里叶变换频谱
6.1.2.2  抖动PSD
6.2  DDJ分离
6.2.1  基于抖动时间函数的分离法
6.2.2  基于傅里叶频谱或PSD的分离法
6.2.3  从DDJ中分离DCD和ISI
6.3  PJ，RJ及BUJ分离
6.3.1  基于傅里叶频谱
6.3.2  基于PSD
6.3.3  基于时域方差函数
6.4  脉宽拉缩
6.4.1  PWS的定义
6.4.2  PWS的平均和DDJ
6.4.3  PWS估计
6.5  时域、频域抖动分离法对比
6.6  小结
参考文献
第7章  时钟抖动
7.1  时钟抖动
7.1.1  时钟抖动的定义
7.1.2  时钟抖动的影响
7.1.2.1  同步系统
7.1.2.2  异步系统
7.2  几种抖动的定义和数学模型
7.2.1  相位抖动
7.2.2  周期抖动
7.2.3  周期间抖动
7.2.4  相互关系
7.2.4.1  时域
7.2.4.2  频域
7.3  时钟抖动与相位噪声
7.3.1  相位噪声
7.3.2  相位抖动到相位噪声的转换
7.3.3  相位噪声到相位抖动的转换
7.4  小结
参考文献
第8章  锁相环抖动及传递函数分析
8.1  锁相环简介
8.2  PLL时域及频域行为
8.2.1  时域建模与分析
8.2.2  频域建模与分析
8.3  PLL功能及参数分析
8.3.1  功能分析
8.3.1.1  相位响应与幅度响应
8.3.1.2  PLL冲激/阶跃响应
8.3.1.3  伯德图
8.3.1.4  极点和零点
8.3.2  参数分析
8.4  PLL抖动及噪声分析
8.4.1  相位抖动功率谱密度(PSD)
8.4.2  方差及PSD
8.5  二阶PLL分析
8.5.1  系统传递函数
8.5.2  特性参数
8.5.3  抖动及传递函数分析
8.5.3.1  基于时域方差函数的方法
8.5.3.2  实验结果
8.6  三阶PLL分析
8.6.1  系统传递函数
8.6.2  特性参数
8.6.3  抖动和传递函数分析
8.6.3.1  基于频域PSD的方法
8.6.3.2  实验结果
8.7  与PLL传统分析方法的对比
8.8  小结
参考文献
第9章  高速链路抖动及信号完整性机理
9.1  链路系统的体系结构与部件
9.2  发送器
9.2.1  发送器子系统体系结构
9.2.2  性能的决定性因素
9.3  接收器
9.3.1  接收器子系统体系结构
9.3.2  接收器性能的决定性因素
9.4  信道或媒质
9.4.1  信道材料和特性
9.4.1.1  铜质信道
9.4.1.2  光纤信道
9.4.2  信道中的其他损耗
9.4.2.1  串扰
9.4.2.2  反射
9.5  参考时钟
9.6  总链路抖动预算
9.7  小结
参考文献
第10章  高速链路抖动及信令完整性的建模与分析
10.1  线性时不变近似
10.2  发送器建模与分析
10.2.1  发送器数据位流
10.2.2  发送器均衡
10.2.3  发送器抖动相位调制
10.2.4  发送器噪声幅度调制
10.2.5  发送器损耗
10.2.6  发送器驱动器
10.3  信道建模与分析
10.3.1  信道线性时不变LTI建模
10.3.2  信道传递函数
10.3.2.1  信道冲激响应
10.3.2.2  信道单位阶跃响应
10.3.2.3  信道S参数
10.3.2.4  S参数、传递函数和反射系数
10.3.3  通用信道模型
10.3.3.1  一阶分析模型
10.3.3.2  二阶分析模型
10.4  接收器建模与分析
10.4.1  接收器损耗
10.4.2  接收器时钟恢复
10.4.3  接收器均衡
10.4.4  接收器参考电压噪声的幅度调制表示
10.4.5  接收器驱动电压噪声的幅度调制表示
10.4.6  接收器驱动器
10.5  小结
第11章  高速链路抖动及信令完整性的测试与分析
11.1  链路信令及其对测试的影响
11.1.1  常态链路信令测试的含义
11.1.1.1  时钟恢复和抖动传递函数
11.1.1.2  抖动传递函数与链路测试
11.1.2  高级链路信令测试
11.1.2.1  发送器均衡与测试
11.1.2.2  接收器均衡与测试
11.2  发送器输出测试
11.2.1  常态串行链路信令的发送器测试
11.2.2  高级串行链路信令的发送器测试
11.2.2.1  发送器均衡的链路信令
11.2.2.2  接收器均衡的链路信令
11.3  信道及信道输出测试
11.3.1  基于S参数的信道测试
11.3.2  带有参考发送器的信道测试
11.4  接收器测试
11.4.1  常态链路信令的接收器测试
11.4.2  高级链路信令的接收器测试
11.4.3  接收器内部抖动测试
11.5  参考时钟测试
11.6  锁相环测试
11.6.1  无激励的测试方法
11.6.2  基于激励的测试方法
11.7  环回测试
11.8  小结
参考文献
第12章  总结与展望
12.1  总结
12.2  展望

winworm

Signal and Power Integrity - Simplified, 2nd Edition已经出版，比第一版增加了12、13章，篇幅增加150页左右。

Table of Contents

Preface to the Second Edition      xv
Preface to the First Edition      xvii
Acknowledgments      xxiii
About the Author      xxv

Chapter 1: Signal Integrity Is in Your Future      1
1.1   What Is Signal Integrity? 2
1.2   Signal Quality on a Single Net 5
1.3   Cross Talk 9
1.4   Rail-Collapse Noise 11
1.5   Electromagnetic Interference (EMI) 13
1.6   Two Important Signal Integrity Generalizations 16
1.7   Trends in Electronic Products 16
1.8   The Need for a New Design Methodology 22
1.9   A New Product Design Methodology 23
1.10 Simulations 24
1.11 Modeling and Models 27
1.12 Creating Circuit Models from Calculation 30
1.13 Three Types of Measurements 35
1.14 The Role of Measurements 38
1.15 The Bottom Line 39

Chapter 2: Time and Frequency Domains      43
2.1   The Time Domain 44
2.2   Sine Waves in the Frequency Domain 46
2.3   Shorter Time to a Solution in the Frequency Domain 48
2.4   Sine Wave Features 49
2.5   The Fourier Transform 51
2.6   The Spectrum of a Repetitive Signal 53
2.7   The Spectrum of an Ideal Square Wave 55
2.8   From the Frequency Domain to the Time Domain 57
2.9   Effect of Bandwidth on Rise Time 58
2.10 Bandwidth and Rise Time 62
2.11 What Does Significant Mean? 63
2.12 Bandwidth of Real Signals 67
2.13 Bandwidth and Clock Frequency 68
2.14 Bandwidth of a Measurement 70
2.15 Bandwidth of a Model 72
2.16 Bandwidth of an Interconnect 74
2.17 The Bottom Line 78

Chapter 3: Impedance and Electrical Models      81
3.1   Describing Signal-Integrity Solutions in Terms of Impedance 82
3.2   What Is Impedance? 84
3.3   Real Versus Ideal Circuit Elements 86
3.4   Impedance of an Ideal Resistor in the Time Domain 88
3.5   Impedance of an Ideal Capacitor in the Time Domain 89
3.6   Impedance of an Ideal Inductor in the Time Domain 92
3.7   Impedance in the Frequency Domain 94
3.8   Equivalent Electrical Circuit Models 99
3.9   Circuit Theory and SPICE 101
3.10 Introduction to Modeling 105
3.11 The Bottom Line 110

Chapter 4: The Physical Basis of Resistance      113
4.1   Translating Physical Design into Electrical Performance 114
4.2   The Only Good Approximation for the Resistance of Interconnects 115
4.3   Bulk Resistivity 118
4.4   Resistance per Length 119
4.5   Sheet Resistance 121
4.6   The Bottom Line 124

Chapter 5: The Physical Basis of Capacitance      127
5.1   Current Flow in Capacitors 128
5.2   The Capacitance of a Sphere 130
5.3   Parallel Plate Approximation 131
5.4   Dielectric Constant 133
5.5   Power and Ground Planes and Decoupling Capacitance 135
5.6   Capacitance per Length 138
5.7   2D Field Solvers 143
5.8   Effective Dielectric Constant 146
5.9   The Bottom Line 150

Chapter 6: The Physical Basis of Inductance      151
6.1   What Is Inductance? 151
6.2   Inductance Principle #1: There Are Circular Rings of Magnetic-Field Lines Around All Currents 152
6.3   Inductance Principle #2: Inductance Is the Number of Webers of Field Line Rings Around a Conductor per Amp of Current Through It 154
6.4   Self-Inductance and Mutual Inductance 156
6.5   Inductance Principle #3: When the Number of Field Line Rings Around a Conductor Changes, There Will Be a Voltage Induced Across the Ends of the Conductor 158
6.6   Partial Inductance 161
6.7   Effective, Total, or Net Inductance and Ground Bounce 167
6.8   Loop Self- and Mutual Inductance 173
6.9   The Power-Distribution Network (PDN) and Loop Inductance 178
6.10 Loop Inductance per Square of Planes 183
6.11 Loop Inductance of Planes and Via Contacts 184
6.12 Loop Inductance of Planes with a Field of Clearance Holes 187
6.13 Loop Mutual Inductance 188
6.14 Equivalent Inductance of Multiple Inductors 189
6.15 Summary of Inductance 191
6.16 Current Distributions and Skin Depth 193
6.17 High-Permeability Materials 202
6.18 Eddy Currents 204
6.19 The Bottom Line 206

Chapter 7: The Physical Basis of Transmission Lines      209
7.1   Forget the Word Ground 210
7.2   The Signal 211
7.3   Uniform Transmission Lines 212
7.4   The Speed of Electrons in Copper 214
7.5   The Speed of a Signal in a Transmission Line 215
7.6   Spatial Extent of the Leading Edge 219
7.7   “Be the Signal” 220
7.8   The Instantaneous Impedance of a Transmission Line 224
7.9   Characteristic Impedance and Controlled Impedance 227
7.10 Famous Characteristic Impedances 230
7.11 The Impedance of a Transmission Line 233
7.12 Driving a Transmission Line 238
7.13 Return Paths 241
7.14 When Return Paths Switch Reference Planes 244
7.15 A First-Order Model of a Transmission Line 257
7.16 Calculating Characteristic Impedance with Approximations 262
7.17 Calculating the Characteristic Impedance with a 2D Field Solver 265
7.18 An n-Section Lumped Circuit Model 270
7.19 Frequency Variation of the Characteristic Impedance 278
7.20 The Bottom Line 279

Chapter 8: Transmission Lines and Reflections       281
8.1   Reflections at Impedance Changes 282
8.2   Why Are There Reflections? 284
8.3   Reflections from Resistive Loads 288
8.4   Source Impedance 290
8.5   Bounce Diagrams 292
8.6   Simulating Reflected Waveforms 295
8.7   Measuring Reflections with a TDR 295
8.8   Transmission Lines and Unintentional Discontinuities 299
8.9   When to Terminate 301
8.10 The Most Common Termination Strategy for Point-to-Point Topology 304
8.11 Reflections from Short Series Transmission Lines 306
8.12 Reflections from Short-Stub Transmission Lines 309
8.13 Reflections from Capacitive End Terminations 311
8.14 Reflections from Capacitive Loads in the Middle of a Trace 314
8.15 Capacitive Delay Adders 317
8.16 Effects of Corners and Vias 319
8.17 Loaded Lines 325
8.18 Reflections from Inductive Discontinuities 327
8.19 Compensation 331
8.20 The Bottom Line 334

Chapter 9: Lossy Lines, Rise-Time Degradation, and Material Properties      337
9.1   Why Worry About Lossy Lines? 338
9.2   Losses in Transmission Lines 340
9.3   Sources of Loss: Conductor Resistance and Skin Depth 342
9.4   Sources of Loss: The Dielectric 346
9.5   Dissipation Factor 351
9.6   The Real Meaning of Dissipation Factor 354
9.7   Modeling Lossy Transmission Lines 360
9.8   Characteristic Impedance of a Lossy Transmission Line 367
9.9   Signal Velocity in a Lossy Transmission Line 369
9.10 Attenuation and the dB 371
9.11 Attenuation in Lossy Lines 376
9.12 Measured Properties of a Lossy Line in the Frequency Domain 385
9.13 The Bandwidth of an Interconnect 390
9.14 Time-Domain Behavior of Lossy Lines 397
9.15 Improving the Eye Diagram of a Transmission Line 400
9.16 Pre-emphasis and Equalization 402
9.17 The Bottom Line 403

Chapter 10: Cross Talk in Transmission Lines      405
10.1   Superposition 406
10.2   Origin of Coupling: Capacitance and Inductance 407
10.3   Cross Talk in Transmission Lines: NEXT and FEXT 409
10.4   Describing Cross Talk 411
10.5   The SPICE Capacitance Matrix 413
10.6   The Maxwell Capacitance Matrix and 2D Field Solvers 417
10.7   The Inductance Matrix 424
10.8   Cross Talk in Uniform Transmission Lines and Saturation Length 425
10.9   Capacitively Coupled Currents 431
10.10 Inductively Coupled Currents 435
10.11 Near-End Cross Talk 438
10.12 Far-End Cross Talk 441
10.13 Decreasing Far-End Cross Talk 448
10.14 Simulating Cross Talk 451
10.15 Guard Traces 457
10.16 Cross Talk and Dielectric Constant 464
10.17 Cross Talk and Timing 466
10.18 Switching Noise 469
10.19 Summary of Reducing Cross Talk 473
10.20 The Bottom Line 474

Chapter 11: Differential Pairs and Differential Impedance      475
11.1   Differential Signaling 476
11.2   A Differential Pair 480
11.3   Differential Impedance with No Coupling 482
11.4   The Impact from Coupling 486
11.5   Calculating Differential Impedance 493
11.6   The Return-Current Distribution in a Differential Pair 496
11.7   Odd and Even Modes 502
11.8   Differential Impedance and Odd-Mode Impedance 507
11.9   Common Impedance and Even-Mode Impedance 508
11.10 Differential and Common Signals and Odd- and Even-Mode Voltage Components 511
11.11 Velocity of Each Mode and Far-End Cross Talk 513
11.12 Ideal Coupled Transmission-Line Model or an Ideal Differential Pair 519
11.13 Measuring Even- and Odd-Mode Impedance 520
11.14 Terminating Differential and Common Signals 522
11.15 Conversion of Differential to Common Signals 529
11.16 EMI and Common Signals 534
11.17 Cross Talk in Differential Pairs 539
11.18 Crossing a Gap in the Return Path 542
11.19 To Tightly Couple or Not to Tightly Couple 544
11.20 Calculating Odd and Even Modes from Capacitance- and Inductance-Matrix Elements 546
11.21 The Characteristic Impedance Matrix 550
11.22 The Bottom Line 553

Chapter 12: S-Parameters for Signal Integrity Applications      555
12.1   S-Parameters, the New Universal Metric 555
12.2   What Are S-Parameters? 557
12.3   Basic S-Parameter Formalism 559
12.4   S-Parameter Matrix Elements 562
12.5   Simulating Return and Insertion Loss 567
12.6   A Transparent Interconnect 570
12.7   Changing the Port Impedance 573
12.8   The Phase of S21 for a Uniform 50-Ohm Transmission Line 574
12.9   The Magnitude of S21 for a Uniform Transmission Line 577
12.10 Coupling to Other Transmission Lines 582
12.11 Insertion Loss for Non-50-Ohm Transmission Lines 589
12.12 Data-Mining S-Parameters 594
12.13 Single-Ended and Differential S-Parameters 596
12.14 Differential Insertion Loss 601
12.15 The Mode Conversion Terms 605
12.16 Converting to Mixed-Mode S-Parameters 607
12.17 Time and Frequency Domains 609
12.18 The Bottom Line 613

Chapter 13: The Power Distribution Network (PDN)      615
13.1   The Problem 615
13.2   The Root Cause 618
13.3   The Most Important Design Guidelines for the PDN 620
13.4   Establishing the Target Impedance Is Hard 621
13.5   Every Product Has a Unique PDN Requirement 629
13.6   Engineering the PDN 631
13.7   The VRM 633
13.8   Simulating Impedance with SPICE 635
13.9   On-die Capacitance 637
13.10 The Package Barrier 639
13.11 The PDN with No Decoupling Capacitors 644
13.12 The MLCC Capacitor 646
13.13 The Equivalent Series Inductance 650
13.14 Approximating Loop Inductance 652
13.15 Optimizing the Mounting of Capacitors 661
13.16 Combining Capacitors in Parallel 667
13.17 Engineering a Reduced Parallel Resonant Peak by Adding More Capacitors 673
13.18 Selecting Capacitor Values 675
13.19 Estimating the Number of Capacitors Needed 681
13.20 How Much Does a nH Cost? 683
13.21 Quantity or Specific Values? 687
13.22 Sculpting the Impedance Profiles: The Frequency Domain Target Impedance (FDTI) Method 692
13.23 When Every pH Counts 699
13.24 Location, Location, Location 703
13.25 When Spreading Inductance Is the Limitation 707
13.26 The Chip View 710
13.27 Bringing It All Together 713
13.28 The Bottom Line 717

Appendix A: 100 General Design Guidelines to Minimize Signal-Integrity Problems      719

Appendix B: 100 Collected Rules of Thumb to Help Estimate Signal-Integrity Effects      727

Appendix C: Selected References      739

Index      741

winworm

第二版序言：

Since the publication of the first edition of Signal Integrity—Simplified, the princi-
ples of signal integrity haven’t changed. What has changed, though, is the prolific
use of high-speed serial links and the critical role power integrity now plays in the
success or failure of new product introductions.
In addition to fleshing out more details and examples in many of the chap-
ters, especially on differential pairs and losses, two new chapters have been added
to this second edition to provide a strong foundation to meet the needs of today’s
engineers and designers.
This first new chapter—Chapter 12—provides a thorough introduction to the
use of S-parameters in signal integrity applications. If you deal with any high-
speed serial links, you will encounter S-parameters. Because they are written in
the foreign language of the frequency domain, they are intimidating to the high-
speed digital designer. Chapter 12, like all the chapters in this book, provides a
solid foundation in understanding this formalism and enables all engineers to har-
ness the great power of S-parameters.
Chapter 13, the second new chapter, is on power integrity. These issues
increasingly fall in the lap of the design engineer. With higher speed applications,
interconnects in the power distribution path affect not just power delivery, but also
signals’ return paths and passing an EMC certification test.
We start at the beginning and illustrate the role of the power distribution
interconnects and how design and technology selection can make or break the per-
formance of the power distribution network. The essential principles of plane
impedance, spreading inductance, decoupling capacitors, and the loop inductance
of capacitors are introduced. This valuable insight helps feed the intuition of engi-
neers enabling them to apply the power of their creativity to synthesize new
designs. Hand in hand with the creation of a design is the analysis of its perfor-
mance so that cost-performance trade-offs can be explored and the PDN imped-
ance profile can be sculpted to perfection.
If you are new to signal integrity, this second edition of Signal and Power
Integrity—Simplified provides your starting place to build a strong foundation and
empowers you to get your new signal integrity designs right the first time, every
time.

jianglanlan461

ding xia

zhangyiyu120

不顶不行。[em01]

winworm

Ansoft Designer V5.0,Nexxim V5.0几个月后将发布，开始支持AMI模型，Agilent ADS也将支持AMI。


MAJOR ENHANCEMENTS Designer V5.0 and Nexxim V5.0
------------------------------------------------

o IBIS AMI support
o Fast transient and eye diagram plotting based on precomputed reports.  Inner
  eye contours optionally plotted.
o Nexxim engine enhancements
  - Improved noise floor for VerifEye
  - Multi-threading for device models and QuickEye/VerifEye step response generation
  - Separate rise/fall times for QuickEye/VerifEye
  - Uniform and periodic transmit jitter in eye sources
  - Engine can be paused during a transient simulation and results can be viewed
  - Faster transient simulations using specialized model topologies
  - Significant S-parameter handing enhancements
o Support for encrypted Verilog (using Ansoft encryption)
o Significantly faster Nexxim tuning and optimization
o PlanarEM
  - Thick conductor Q factor enhancements
  - Via modeling improvements
  - Improved adaptive refinement algorithm
  - Post processing variables
  - Improved simulation data management for better performance
o Common and differential mode plotting for Nexxim and PlanarEM
o Filter design and synthesis tool.
  - Designs can be exported ready-to-simulate to Nexxim
o New tab in model definitions that allows users to pre-configure symbol
  pin locations when auto generating symbols
o Caching of state-space fit models NPort models for use across projects
o Parametric snapshot available for HFSS transmission line models
o New solver-on-demand configurations to set multiple solver-on-demand settings
  at the project level in one shot
o Ports and source "configurations" for Nexxim projects that provide better
  source management capabilities
o File open preview shows thumbnail view of designs, notes and whether solved or not
o Hierarchy now supported in PlanarEM
o Layout stackup editor shows a preview of the stackup
o Schematic editor has a new design list facility that lists components, graphics,
  ports and nets.  Allows easy selection and property editing.
o New padstack editor
  - top and cross section preview with tool tips
  - in-place editing with true layers from current layout
o ndExplorer enhancements
  - Cell filtering to access only particular matrix entries
  - Log x axis scaling
  - Support for differential and singled ended matrices
  - Gamma and port impedance piloting
  - Enhancements when working with multiple files at the same time
o Support for arrays of text and parametric sweeps
  - Bit patterns, W-elements and S-elements
  - Methods to import arrays of text from .cvs & .txt files
o Wizard to create swept S & W element models
o HFSS Export
  - ability to draw the air box and dielectric extents on the user layer in
    Designer and use this information at export time
  - ability to define the air box side as a dynamic factor
  - added support for parametric line export
  - added ability to automatically export instantiated geometry and simulate
    when necessary
  - added a property on ports and pins to specify reference ground layer for
    HFSS export  
o Miscellaneous
  - Optional property callback triggered on variable changes
  - Various layout import enhancements
  - Expanded on-line help
  - Additional examples in on-line help
  - New Ansoft COM technology for easier DSO setup and better integration
    with third party schedulers

drjiachen

版主发布的信息很新啊

winworm

Ansys HFSS 12.0正式发布，重大更新包括64bit网格剖分、TAU网格技术、域分解，更适合多核CPU系统：

ANSYS Releases HFSS 12.0 Engineering Simulation Software
Industry-Standard RF & Microwave Simulation Solution Delivers Significant New Domain Decomposition Technology for High-Performance Computing

SOUTHPOINTE, Pa., Sep 17, 2009 (BUSINESS WIRE) -- ANSYS, Inc. (NASDAQ: ANSS), a global innovator of simulation software and technologies designed to optimize product development processes, today announced the release of HFSS(TM) 12.0 software, the industry-leading technology for 3-D full-wave electromagnetic field simulation. The product, part of the Ansoft suite, helps engineers design, simulate and validate the behavior of complex high-performance radio frequency (RF), microwave and millimeter-wave devices in next-generation wireless communication and defense systems. A key high-performance computing (HPC) enhancement, domain decomposition, allows engineers to simulate and design at a scale and speed never before possible. Users of this latest version of HFSS software can achieve a dramatic reduction in development time and costs while at the same time realizing increased reliability and design optimization.

With the release of HFSS 12.0, ANSYS follows through on its commitment to deliver technology with unequalled depth and unparalleled breadth. HFSS 12.0 is a major step forward for three-dimensional full-wave electromagnetic field simulation. The software includes key updates in mesh generation, solver technologies, and enhancements to the user interface and the modeler. A new, faster and more robust meshing algorithm generates higher-quality, more efficient tetrahedral meshes. The most significant solver technology enhancement is domain decomposition, a technique that allows HFSS to exploit HPC capabilities to solve electromagnetic field problems of unprecedented size and scope. Other important enhancements include mixed element orders, curvilinear elements, and adjoint derivative computation. Ease of use and automation in the user interface have been improved and include additional modeler capabilities such as sheet wrapping and imprinting. These advances in HFSS 12.0 enable electrical engineers to expand their solution capability, exploit HPC hardware and fully integrate electromagnetics analysis into their Simulation Driven Product Development(TM) processes.

"HFSS 12.0 is a breakthrough in high-frequency electromagnetic field simulation," said Zol Cendes, chief technology officer and general manager at Ansoft. "For the first time, engineers are able to solve vast electromagnetic field problems with speed, efficiency and accuracy. Because of domain decomposition, microwave and electronics engineers now have the opportunity to successfully address a new range of problems containing hundreds of millions of unknowns that previously could not be addressed by simulation. The ANSYS focus on developing simulation technology that takes full advantage of modern computer hardware solutions means that customers will have future capabilities that, today, we can only imagine."

The new domain decomposition technology in HFSS 12.0 software allows efficient and highly scalable parallelized simulations across multiple computer cores including networked cores. In running a 15-GB benchmark on an HP 7880 workstation, domain decomposition using eight cores exhibited an 8.8-times speedup with a 33 percent memory savings compared to a single-core direct solve.

Curvilinear elements and mixed element orders allow for higher accuracy and more efficient distribution of computational resources. Curvilinear elements model the fields exactly on curved surfaces and in these cases provide higher accuracy even with a coarser mesh discretization. Mixed element orders allows for an automated and judicious localized application of element order. Smaller features are solved more efficiently by lower-order elements while large homogenous regions benefit from higher-order elements, all element orders being automatically and appropriately "mixed" in one mesh.

Molex Incorporated, a leading supplier of electronic connectors and interconnect products, was among the organizations that participated in beta testing the new release. The company investigated a number of features, including the new TAU volumetric meshing technique, whose robust tet mesh elements reduce the overall load on the solver. "The new TAU meshing and mixed element orders technology in HFSS 12.0 will allow Molex engineers to more accurately and efficiently simulate and design," said Dave Dunham, engineering director at Molex. "We have more than doubled productivity with the implementation of HFSS 12.0 in our design flow."

Adjoint derivative computation provides a highly efficient and accurate procedure to evaluate the derivatives of S-parameters with respect to geometric and material model parameter variations. This technique provides sensitivity information for use in device tuning, tolerance evaluation and optimization. These derivatives are employed to speed up the sequential nonlinear programming (SNLP) optimizer included with the Optimetrics(TM) add-on program.

New features in HFSS 12.0 software include:

    * New TAU meshing technology
    * Domain decomposition solver technology
    * Curvilinear elements
    * Mixed element orders
    * Adjoint derivative computation
    * Update to ACIS R19.2
    * Improved link with ANSYS(R) DesignXplorer(TM) software








                             HFSS(tm) v12.0                       
                    ==================================
                              Ansoft, LLC
                 225 West Station Square Dr, Suite 200
                     Pittsburgh, PA 15219-1119 USA

This file contains important information regarding the installation and
use of HFSS(tm).  When appropriate, late-breaking information is
provided herein that could not be included in the software documentation.  


32-bit System Requirements
==========================
Minimum System Requirements:
Processor: All fully compatible 686 (or later) instruction set processors, 500 MHz
Hard Drive Space (for HFSS software): 200 MB
RAM: 512 MB 

Recommended Minimum Configuration (for Optimal Performance):
Processor: All fully compatible 786 (or later) instruction set processors, 2 GHz
Hard Drive Space (for HFSS software and temporary files): 700 MB
RAM: 4 GB 

64-bit System Requirements
==========================
Minimum System Requirements:
Supported processors: AMD Athlon 64, AMD Opteron, Intel Xeon with Intel EM64T
                      support, Intel Pentium 4 with Intel EM64T support
Hard Drive Space (for HFSS software): 200 MB
RAM: 2 GB 

Recommended Minimum Configuration (for Optimal Performance):
Supported processors: AMD Athlon 64, AMD Opteron, Intel Xeon with Intel EM64T
                      support, Intel Pentium 4 with Intel EM64T support
Video card: 128-bit SVGA or PCI Express video card
Hard Drive Space (for HFSS software and temporary files): 700 MB
RAM: 8 GB 

Supported Operating Systems: 
- Windows XP 32-bit Service Pack 2
- Windows Server 2003 32-bit Service Pack 1
- Windows Vista 32-bit Service Pack 1

- Windows XP 64-bit Service Pack 2
- Windows Server 2003 64-bit Service Pack 1
- Windows HPC Server 2008
- Windows Vista 64-bit Service Pack 1


Installation
============
This CD contains the following installation options:
- Install HFSS: Use this option to install HFSS(tm) on your local machine.

- Install Libraries: Use this option to install the libraries
on any machine that HFSS can see from the network.  Installing the libraries
on a remote machine allows multiple users to share a common
HFSS libraries database.

Note: If you want to install the HFSS libraries on your local machine,
you can do so during the HFSS software installation.

- Install Remote Simulation Manager: Use this option to install Remote
Simulation Manager on your local machine. 


Temp Directory Prompt
---------------------
There is a new dialog in the HFSS installation that prompts you for
a temporary directory to be used by default for all users.  You can override
the setting for a specific user by using the Tools > Options > General Options
menu and selecting the Override checkbox associated with the Temp Directory setting.

If you wish to edit the default setting, for now you must modify the installation.


Installation Maintenance
------------------------
If you need to modify the RSM settings after the installation is complete, you
can run the installation in maintenance mode by choosing Start > Programs >
Ansoft > Remote Simulation Manager > Remote Simulation Manager Maintenance.



Technical and Installation Support
==================================
For installation or technical support, please send e-mail to techsupport@ansoft.com
or call (+1) 412-261-3200 x199.

Please provide the following information when you contact us:  
  - Your name and affiliation  
  - Version number of HFSS  
  - The type of hardware and operating system you are using  
  - A description of what happened and what you were doing when the    
    problem occurred as well as the exact wording of any messages    
    that appeared on the screen 

HFSS project files (.hfss) are ASCII text and can be sent by e-mail.  



Known Problems, Workarounds, and Undocumented Features
======================================================

General
-------
1) ANSft00089261: It is possible to encounter a desktop crash when a user selects
the 'Families' tab in a report setup.  This is only a problem on Windows, and it
can occur when mfc80.dll has been upgraded to a newer version.  Microsoft has made
a hotfix available at the following website, http://support.microsoft.com/kb/961894.
 

HFSS-specific issues
--------------------
1) Mixed Order
     - The fields post-processor only supports a single order, and fields are
       written out at the highest order used in the solution.

2) Matched terminals
     - Users must obtain a build of Ansoft Designer 4.1.1 in order to link with
       a driven terminal design in HFSS 12.0.

3) Analytical derivatives
     Driven Modal Projects:
        - Parameterized ports with degenerate modes 
        - Parameterized analytical ports
        - Parameterized master/slave boundary conditions

4) Remote Simulation Manager
     - RSM should not be installed to a mapped network drive.
    
5) Datalink
     - The link to Ansoft Designer will not support post-processing variables for the
       HFSS 12.0 release.
      
ANSft00090009: HFSS/HFSS near-field datalink simulations will fail when the source
           design contains two symmetry planes.



Version 12.0 Major Enhancements
===============================
Meshing:
- TAU mesher
- 64-bit meshing 
- Curvilinear mesh elements

Solve:
- Domain decomposition
- Analytical derivatives
- Mixed-order solutions
- Matched terminal port solutions
- Extended precision for port solutions
- Two-way thermal analysis link with ANSYS Mechanical *

Remote Simulation and Distributed Solve:
- New remote simulation manager (RSM)
- Supports LSF and Windows HPC

Optimetrics:
- Integration with ANSYS DesignXplorer *

Excitation Setup:
- Enhanced analytical polarization of modes   
- Mode filtering for report setup

Desktop:
- Project preview
- Integrated crash reporting
- Hotkey customization

Modeler:
- ACIS 19 SP2
- Select by area
- Flexible history editing
- Defineable width for polyline cross-section
- Moveable sheet edges
- View model sections
- Wrap sheet around a solid
- 2D fillets and chamfers
- Imprint sheet on solid
- Enhanced healing: stitch and merge faces

Post-Processing:
- Post processing variables
- Expression cache for solve setup
- Report display types: stacked plots, rectangular contour plots, enhanced data
  tables
- Streamline field plots


* Available upon release of ANSYS 12.1

winworm

Hspice 2009.9发布，在SI方面的升级包括StatEye、S参数处理的多线程支持、去嵌、8B10B码源。

64bit Linux是目前能够充分计算机资源最好的Hspice仿真平台，支持32bit、64bit，而Win下只有32bit，同时支持多处理器、多线程，而Win下只支持多线程。

Performance, Convergence, Capacity and Accuracy
Improvements
■ Improved DC auto convergence for analog circuits
See HSPICE Reference Manual: Commands and Control Options,.OPTION
CONVERGE =100 new adaptive auto-convergence algorithm that improves
the performance and robustness of DC operating point calculation.
■ Improved capacity: Up to 5M elements with 500K MOS.
■ Improved runtime performance for standard cell characterization (1.5X
speedup compared with HSPICE B-2008.09).
■ Multiprocessing and Multithreading simultaneously on Linux.
See HSPICE User Guide: Simulation and Analysis, Chapter 3, Startup and
Simulation, section “Running Multithread/Multiprocess HSPICE
Simulations.” This release also introduces multiprocessing in the advanced
client-server mode; see section “Launching the Advanced Client/Server
Mode (-CC).”

Ease of Use
■ Improved *.lis file, simplifying simulation reporting, and enabling separation
of warnings/errors into their own log files for more efficient troubleshooting.
See the HSPICE Reference Manual: Commands and Control Options,  
.OPTION LIS_NEW and .OPTION WARN_SEP.
■ Improved error/warning messages and syntax checking; continued
improvement in the ongoing project to provide more usable error/warning
messages.
See Appendix E, HSPICE User Guide: Simulation and Analysis for updates
to strict parser requirements, and the section “Reserved Keywords” in
Chapter 4, Input Netlist Data Entry.
■ HSPICE and HSPICE RF integration into a single binary executable.
See HSPICE User Guide: RF Analysis, Chapter 1.
■ Improved Launcher Options window for HSPUI enables users to customize
configurations according to their preferred locations.
See Configuring the HSPICE GUI for Windows in Chapter 6 of the HSPICE
User Guide: Simulation and Analysis.

Signal Integrity
■ Statistical Eye Diagram—.STATEYE—numerous enhancements, including:
•  Non-linear buffer extension
•  Emphasizing and encoding for incident ports
•  Deterministic jitter additions
See HSPICE User Guide: Simulation and Analysis, Chapter 18: Statistical
Eye Analysis.
■ S-element rational function generation process multithread capability.
■ S-parameter de-embedding.
See HSPICE User Guide: Signal Integrity, Chapter 2: S-parameter Modeling
Using the S-element.
■ 8b10b encoding support for Pattern and Pseudo Random-Bit Generator,
and P-element Sources.
See HSPICE User Guide: Simulation and Analysis, Chapter 9: Sources and
Stimuli and the Documentation Addenda in this release note.