业界观察

winworm

5月15日，Sisoft发布2008.04版本，主要更新针对DDR3：

Release Notes:
Signal Integrity Software, Inc. is pleased to release Version 2008.04 of SiSoft software.
This document contains the release notes for this version of software.
Note: Starting with version 2008.04, SiSoft software products are released and installed
together. See the Installation Guide for information on the new default install path.


Enhancements in 2008.04:
• Quantum-SI Enhancements
– Support for training in timing models (DDR3)
– Reporting of untrained, optimum and trained timing margins
– Support for matching DQS designators to CK designators in pre-layout
(DDR3)
– Tvac waveform parameter (Time beyond AC threshold) (DDR3)
– New slew rate measurement |SiSoft parameters: derate_min_slew,
derate_max_slew, diff_derate_min_slew, diff_derate_max_slew
– Split plane support for Board Station and PADS
– Support for WIRES in Allegro MCM files
– Access to Part Details from Assignment Details dialog. Right-click on row
of Assignment Details allows Part details to be shown.
• SiViewer Enhancements
– Named eye masks
– Fatal, Overshoot and Quality violations can be shown on waveforms

winworm

很遗憾，找了一圈，ADS2008 Update1中只能生成冲激响应的波形，没发现能用冲激响应进行瞬态仿真的功能.

 从s参数得到冲激响应：

冲激响应波形：

已经得到确切消息，将会在2008第二个升级版本中提供Imp的仿真功能。

[此贴子已经被作者于2008-5-22 20:30:27编辑过]

winworm

今天给大家介绍一个Spice网表图形化的工具：SpiceVision
支持的Spice网表格式有：Spice2、Spice3、Pspice、Hspice、cdl、calibre，当然，我们最关心的是对Hspice的支持，以前老版本有部分hspice的器件不支持，目前已经提供对Hspice的完全支持，下图是Xilinx Virtex 5 SI Kit TestBench的图形化结果。

SpiceVision PRO takes the complex SPICE descriptions produced by many EDA tools and generates clean, easy-to-read transistorlevel schematics and circuit fragments, and design documentation to speed up debugging and project development. Spice circuits and models are the common currency of the EDA world. They are generated by many EDA tools and provide a description of the circuit at the lowest level of components: the transistors, capacitors, resistors and even the interconnect, that combine to produce, for example, an IC. But for all but the most trivial design, Spice files are difficult to read. SpiceVision generates circuit schematics on screen and speeds up debugging and project development. The SpiceVision product family helps to solve design problems in: Digital Circuits, Mixed-Signal ASICs, Analog Circuits, Printed Circuit Boards and MEMS.

Click here to see higher resolution picture

    * Graphical netlist analyzer — pre-layout and post-layout SPICE
    * Tcl based UserWare API — for advanced customization
    * 32/64-bit database handles today′s largest SoCs and ASICs
    * Exports schematics and schematic fragments — Cadence Virtuoso and EDIF 2.0.0
    * Cone display — Cone Window displays selected fragments and critical paths
    * Cookie-cutting — fragments can be saved as separate SPICE files

winworm

StaeEye V5 Beta

完全用Python重写，彻底的开放源码，可以在这里下载 http://www.stateye.org/ 

目前已经有Agilent ADS、Ansoft Nexxim、Cadence SigXp中支持统计眼图分析。

Specification:

Data Input

Step input from scope

Initially a single step response time record will be requried
For more complex transmitter signals the use of a penrose matrix inversion can lead to multiple step responses representing the transmitter, however, I would suggest we leave this for now
The support of simple step responses is already supported in the XML definition language of v4.2.2. The support of multiple steps is open.
more details of this interface are discussed here
S-Parameters

all the features from v4 (8×8, mapping, cascading, interpolation, ifft), currently all available in the GUI and XML
wizard for SATA, clearly is a new feature, and some .net features have been tried out already by Edotronik
investigation of padding requirements and bandwidth requirements for 25Gbps under investigation, needs additional option in XML and GUI
Language Support

python suport for all necessary machines OS done
use of numpy for all necessary math functionality done
support of necessary graphical output using matplotlib almost complete
Jitter Definition

Pulse Width Shrinkage support using time correlated edge jitter shall be initially defined in terms of a simple bimodal peak to peak jitter.
Further definition of a time correlated jitter is under discussion with the Technische University München
Mid band jitter shall be calculated as in v4. The engine shall accept as an input a histogram description of the jitter distribution. (Higher level functionality in the GUI or scope should be responsable for conversion of RJ/DJ to pdfs.
Coding and emphasis

All combination are theorically possible, however, each combination needs a new state transition definition therefore a limited number of combinations should be implemented, exact combination to be define. GUI and XML should be changed to
cover equalisation using a single object as opposed to a transmitter and receiver object (exact details under discussion, e.g. interpretation of old xml files)
8b10b; discussion still ongoing concerning exact state transition table
nrz; no problems
duobinary; needs pre-coder, however exact coder/decoder not clear
pam4; including pre-coder clear, however, decision level for receiver not clear. No PAM-n.
lte; adaption algorithm in v4, as per OIF, was very unsatisfactory, method should be done using convolution of the step response and adaption as below
dfe; as per v4. Support for PAM-4 or duobinary currently unclear
fir (de-emphasis); as per v4, however, not all combinations with other schemes clear
current optimisation using simplex algorithm and eye opening may not be enough, therefore move to more theoritical zeroing of partial or full cursors in step response may be preferable. Would allow faster analysis, and maybe more stable results. Crosstalk ISI should be included using a peak distortion minimisation.
all equalisation shall be implemented as analytic solution directly on the pulse/impuse response, i.e. not looping the stateye engine
Some additional requests

padding for ifft should be function of the fbaud
can the time interpolation be removed, as we now have such a large fmax?
can fractional fir be supported
for DFE/CDR analysis can the edge also be well analysed
does FIR @ the Tx = FIR @ the Rx

Stateye 仿真得到的通道冲激响应和阶跃响应;

 

通道的Sdd21曲线：

 

统计眼图;

[此贴子已经被作者于2008-6-8 20:21:01编辑过]

howsi

QUOTE:

以下是引用winworm在2008-5-20 23:09:00的发言：

很遗憾，找了一圈，ADS2008 Update1中只能生成冲激响应的波形，没发现能用冲激响应进行瞬态仿真的功能.

 从s参数得到冲激响应：

冲激响应波形：

已经得到确切消息，将会在2008第二个升级版本中提供Imp的仿真功能。

在IBIS-AMI模型等成为标准后才会有实际的应用。

howsi

QUOTE:

以下是引用winworm在2008-6-8 19:06:00的发言：

StaeEye V5 Beta

完全用Python重写，彻底的开放源码，可以在这里下载 http://www.stateye.org/ 

目前已经有Agilent ADS、Ansoft Nexxim、Cadence SigXp中支持统计眼图分析。

Specification:

Data Input

Step input from scope

Initially a single step response time record will be requried
For more complex transmitter signals the use of a penrose matrix inversion can lead to multiple step responses representing the transmitter, however, I would suggest we leave this for now
The support of simple step responses is already supported in the XML definition language of v4.2.2. The support of multiple steps is open.
more details of this interface are discussed here
S-Parameters

all the features from v4 (8×8, mapping, cascading, interpolation, ifft), currently all available in the GUI and XML
wizard for SATA, clearly is a new feature, and some .net features have been tried out already by Edotronik
investigation of padding requirements and bandwidth requirements for 25Gbps under investigation, needs additional option in XML and GUI
Language Support

python suport for all necessary machines OS done
use of numpy for all necessary math functionality done
support of necessary graphical output using matplotlib almost complete
Jitter Definition

Pulse Width Shrinkage support using time correlated edge jitter shall be initially defined in terms of a simple bimodal peak to peak jitter.
Further definition of a time correlated jitter is under discussion with the Technische University München
Mid band jitter shall be calculated as in v4. The engine shall accept as an input a histogram description of the jitter distribution. (Higher level functionality in the GUI or scope should be responsable for conversion of RJ/DJ to pdfs.
Coding and emphasis

All combination are theorically possible, however, each combination needs a new state transition definition therefore a limited number of combinations should be implemented, exact combination to be define. GUI and XML should be changed to
cover equalisation using a single object as opposed to a transmitter and receiver object (exact details under discussion, e.g. interpretation of old xml files)
8b10b; discussion still ongoing concerning exact state transition table
nrz; no problems
duobinary; needs pre-coder, however exact coder/decoder not clear
pam4; including pre-coder clear, however, decision level for receiver not clear. No PAM-n.
lte; adaption algorithm in v4, as per OIF, was very unsatisfactory, method should be done using convolution of the step response and adaption as below
dfe; as per v4. Support for PAM-4 or duobinary currently unclear
fir (de-emphasis); as per v4, however, not all combinations with other schemes clear
current optimisation using simplex algorithm and eye opening may not be enough, therefore move to more theoritical zeroing of partial or full cursors in step response may be preferable. Would allow faster analysis, and maybe more stable results. Crosstalk ISI should be included using a peak distortion minimisation.
all equalisation shall be implemented as analytic solution directly on the pulse/impuse response, i.e. not looping the stateye engine
Some additional requests

padding for ifft should be function of the fbaud
can the time interpolation be removed, as we now have such a large fmax?
can fractional fir be supported
for DFE/CDR analysis can the edge also be well analysed
does FIR @ the Tx = FIR @ the Rx

Stateye 仿真得到的通道冲激响应和阶跃响应;

 

通道的Sdd21曲线：

 

统计眼图;

SiSoft 即将推出的Quantum Channel Designer在统计眼图分析方面也不错

winworm

Agilent的Imp仿真功能不需要IBIS AMI的支持，有了这个功能可以马上用起来，可以结合托勒密引擎完成串行链路仿真。

SiSoft 的Quantum Channel Designer目前还是个摆设，不知道如何去用，在Sisoft 2008.4 Sp1中只有软件模块，缺少配套的帮助文档，目前的QCD_Users_Guide.pdf基本上没啥实质性内容，QCD_Tutorials.pdf根本就是个空白，也没有tutorial，可能会在下一版本中改善。

QCD的界面：

[此贴子已经被作者于2008-6-21 13:59:06编辑过]

winworm

Power Distribution Network Design Methodologies

by Istvan Novak (Author)
# Paperback: 544 pages
# Publisher: International Engineering Consortium (May 5, 2008)
# Language: English
# ISBN-10: 1931695652
# ISBN-13: 978-1931695657
# Product Dimensions: 8.9 x 6 x 1.2 inches

This book is the most complete, most thorough book that I have ever seen on the rapidly evolving field of power integrity (PI), which includes contributions from nearly 50 noted experts at well-known electronics manufacturers, consultants, and universities. Instead of presenting the one best solution, it offers a variety of viewpoints and discusses the complexity of building products, product cost, and their robustness against design and manufacturing errors. --John Barnes, Owner, dBi Corporation

Dr. Istvan Novak has brought together industry experts of signal integrity and EMI to share their perspectives on power delivery design and experiences in optimizing the design of the power distribution network. This book covers the collected wisdom of the industry as reported over the last 10 years. If your work involves the power delivery network, this is a must-have. --Eric Bogatin, President, Bogatin Enterprises, LLC

A comprehensive book on power distribution networks (PDN) and power integrity (PI) has been in need for some time, and this monumental volume by Dr. Novák is one of the best on this subject. This book brings tremendous and tangible value to anyone who has the interests in, or is already working on, these ever-evolving and intriguing fields. --Mike Peng Li, Principal Architect and Distinguished Engineer, Altera Corporation

Product Description
Power Distribution Network Design Methodologies is a collection of cogently written articles by 49 industry experts that fills in the void on PDN design procedures, and addresses among others such related topics as DC-DC converters, selection of bypass capacitors, DDR2 memory systems, powering of FPGAs, synthesis of impedance rofile. Through each of these contributions from such leading companies as SUN Microsystems, Sanyo, IBM, Hewlett-Packard, Intel, and Rambus, the reader can come to understand why books on power-integrity are only now becoming available to the public and can relate these topics to current industry trends.

Power Distribution Network Design Methodologies is a collection of cogently written articles by 49 industry experts that fills in the void on PDN design procedures, and addresses among others such related topics as DC-DC converters, selection of bypass capacitors, DDR2 memory systems, powering of FPGAs, synthesis of impedance profile. Through each of these contributions from such leading companies as SUN Microsystems, Sanyo, IBM, Hewlett-Packard, Intel, and Rambus, the reader can come to understand why books on power-integrity are only now becoming available to the public and can relate these topics to current industry trends.

About the Author

Istvan Novak is a distinguished engineer of signal and power integrity at Sun Microsystems. He is a fellow of IEEE for his contributions to signal-integrity modeling, measurements, and simulations. Dr. Novak has been working on high-speed signaling and power distribution designs of Sun's V880, V480, V890, V490, T1000, T2000, T5120 and T5220 mid-range server families.

His new technology development work with laminate suppliers, printed-circuit fabricators and component vendors resulted in the introduction of the first sub 2-mil laminates and controlled-ESR bypass capacitors for Sun servers.

Dr. Novak developed a new validation methodology for the measurement of a wide range of power-distribution components, such as DC-DC converters, bypass capacitors and printed-circuit-board power-ground laminates. The methodology has been presented in several conference papers, two of which won the best paper awards.

Dr. Novak carries 24 years of international consulting and instructing experience, and 28 years of design experience in the field of high-speed and high-frequency circuits and systems. He is an international consultant and instructor with 30 years of experience in the field of high-speed and high-frequency circuits and systems. Dr. Novak holds 25 patents in power distribution, signal integrity, and digital signal processing, is the co-author of "Frequency-Domain Characterization of Power Distribution Networks," and he has published more than 100 technical papers.

Dr. Novak has worked and consulted for several companies in the computer and telecommunications industry, to do clock- and power-distribution networks, switching-mode converters as well as various high-speed backplanes, PCI buses, and copper and optical interconnects in the GB/s range.
Dr. Novak obtained his Ph.D. degree from the Hungarian Academy of Sciences, and he received his technical education from the Technical University of Budapest.

Part I

Chapter 1: Power Supply Compensation for Capacitive Loads
Jonathan L. Fasig, Principal Engineer, Mayo Clinic
Barry K. Gilbert, Director, Mayo Clinic
Erik S. Daniel, Deputy Director, Mayo Clinic
1.1: Abstract
1.2: Introduction
1.3: System Overview
1.4: Power Supply Stability Primer
1.5: Analysis
1.6: Conclusion

Chapter 2: DC-DC Converters: What is Wrong with Them?
Istvan Novak, Senior Signal Integrity Staff Engineer, Sun Microsystems
2.1: Abstract
2.2: Introduction
2.3: DC-DC Converter Parameters Related to Signal Integrity
2.4: Potential SI Problems from the User's Perspective
2.5: Conclusion

Chapter 3: The Advantage of Controlled-ESR Polymer Capacitators
Hideki Ishida, Design and Application Section Manager, Sanyo Electric Co.
3.1: Abstract
3.2: Controlling ESR Value of Tantalum Polymer Capacitor
3.3: Importance of Controlled ESR Value Capacitor
3.4: Tantalum Polymer Capacitor with DC/DC Converter Switching in the MHz Range
3.5: Equivalent Circuit of Polymer Tantalum Capacitor

Chaper 4: ESR-Controlled MLCCs and Decoupling Capacitor Network Design
Masaaki Togashi, Senior Development Engineer, TDK Corp.
Chris Burket, Senior Applications Engineer, TDK Corp.
4.1: Abstract
4.2: Introduction
4.3: Decoupling Capacitor Network
4.4: ESR and ESL
4.5: ESR Control Method
4.6: ESR/ESL Measurement of MLCCs
4.7: Measurement Results
4.8: Circuit Analysis using SPICE Simulation
4.9: Lower ESL Development
4.10: Conclusion

Part II

Chapter 5: A Power Distribution System
K. Barry A. Williams, Principal Engineer, Hewlett-Packard
5.1: Abstract
5.2: An Example of a Power Distribution Design System
5.3: The Problem Schematic
5.4: The Characterization of the Load
5.5: System Bandwidth
5.6: Determination of the Maximum Impedance
5.7: The Q of the System
5.8: Capacitance and Inductance Determination
5.9: Resonant Frequency Points
5.10: Number of Capacitors
5.11: Summary of Compiled Results
5.12: Summary of the Capacitor Selections and Graphical Selections
5.13: Graphics Results with Added Resistance
5.14: Sensitivity
5.15: Summary of the Design

Chapter 6: Designing Minimum Cost VRM8.2/8.3 Compliant Converters
Richard Redl, President, ELFI S.A.
Brian Erisman, Project Engineer, Analog Devices, Inc.
6.1: Abstract
6.2: Introduction
6.3: Objective Specifications
6.4: Load Transient Performance Limits of the Buck Converter
6.5: Optimal Load Transient Response
6.6: Commonly Used Control Techniques
6.7: Design for Optimal Output Impedance
6.8: Computer Simulations and Experimental Results
6.9: Summary

Chapter 7: Frequency Domain Target Impedence Method for Bypass Capacitator Selection for Power Distribution Systems
Larry D. Smith, Principal Signal Integrity Engineer, Altena Corp.
7.1: Abstract
7.2: Introduction
7.3: Target Impedance
7.4: Impedance in the Frequency Domain
7.5: PCB Bypass Capacitor
7.6: Capacitor Sizing from Target Impedance and Corner Frequency
7.7: ESR Considerations
7.8: Problems at High and Low Frequency
7.9: Comparing FDTIM to Other Methods
7.10: Conclusion

Chapter 8: Resonant-Free Power Network Design Using Extended Adaptive Voltage Positioning Methodology
Alex Waizman, Principal Engineer, Intel Corp.
Chee-Yee Chung, Principal Engineer, Intel Corp.
8.1: Abstract
8.2: Introduction
8.3: Lumped Power Delivery Model
8.4: Adaptive Voltage Positioning
8.5: EAVP
8.6: Time Domain Results
8.7: Future Work
8.8: Summary

Chapter 9: Distributed Matched Bypassing for Board-Level Power Distribution Networks
Istvan Novak, Senior Staff Engineer, Sun Microsystems
Leesa Noujeim, Staff Engineer, Sun Microsystems
Valerie St. Cyr, Supply Base Development Manager, Sun Microsystems
Nick Biunno, Principal Engineer, Sanmina-SCI
Atul Patel, Process Engineer, Sanmina-SCI
George Korony, Senior Member of Technical Staff, AVX Corp.
Andy Ritter, Senior Member of Technical Staff, AVX Corp.
9.1: Abstract
9.2: Introduction
9.3: Distributed Matched Bypassing of Power Distribution Networks
9.4: Implementation of Distributed Matched Bypassing
9.5: The Concept of the Bypass Resistor
9.6: Conclusion

Part III

Chapter 10: Comparison of Power Distribution Network Design Methods: An Approach to System-Level Power Distribution Analysis
Dale Becker, Senior Technical Staff Member, IBM Corp.
10.1: Abstract
10.2: Introduction
10.3: A Computer System
10.4: Power Distribution Noise Analysis
10.5: Summary

Chapter 11: Bypass Filter Design Considerations for Modern Digital Systems, a Comparative Evaluation of the Big "V," Multipole, and Many Pole Bypass Strategies
Steve Weir, Consultant, Teraspeed Consultant Group
11.1: Abstract
11.2: What Does the Bypass Network Do?
11.3: Multilayer Chip Capacitor Bypass Basics
11.4: Bypass Strategies--Three Methods, Three Faiths?
11.5: Summary
11.6: Conclusion

Chapter 12: Comparison of Power Distribution Network Design Methods: Bypass Capacitator Selection Based on Time Domain and Frequency Domain Preferences
Istvan Novak, Senior Signal Integrity Staff Engineer, Sun Microsystems
12.1: Abstract
12.2: Introduction
12.3: So, What Is the Metric?
12.4: Comparison of Popular Methods Based on Lumped Self-Impedance
12.5: Component Placement
12.6: Implementation Examples
12.7: Conclusion

Chapter 13: PDN Design Strategies: Ceramic SMT Decoupling Capacitators--What Values Should I Choose?
James L. Knighten, Senior Staff Engineer, NCR Corp.
Bruce Archambeault, Distinguished Engineer, IBM
Jun Fan, Senior Hardware Engineer, NCR Corp.
Giuseppe Selli, Ph.D. Candidate, University of Missouri-Rolla
Samuel Connor, Senior Engineer, IBM
James L. Drewniak, Professor, University of Missouri-Rolla
13.1: Introduction
13.2: The Power Bus Function
13.3: The Decoupling Capacitor
13.4: Interconnect Inductance
13.5: Conclusion

Part IV

Chapter 14: Power Integrity Analysis of DDR2 Memory Systems during Simultaneous Switching Events
Ralf Schmitt, Signal Integrity Engineer, Rambus, Inc.
Joong-Ho Kim, Signal Integrity Engineer, Rambus, Inc.
Chuck Yuan, Signal Integrity Engineer, Rambus, Inc.
June Feng, Signal Integrity Engineer, Rambus, Inc.
Woopoung Kim, Signal Integrity Engineer, Rambus, Inc.
Dan Oh, Signal Integrity Engineer, Rambus, Inc.
14.1: Abstract
14.2: Introduction
14.3: Supply Noise Modeling Methodology for Interface Systems
14.4: SSN Model for DDR2 Test System
14.5: Determining Worst-Case Switching Profiles
14.6: Correlating Supply Noise Parameters
14.7: Measuring Supply Noise on Internal Supply Voltage
14.8: Summary

Chapter 15: Analysis of Supply Noise Induced Jitter in Gigabit I/O Interfaces
Ralf Schmitt, Signal Integrity Engineers, Rambus, Inc.
Hai Lan, Signal Integrity Engineer, Rambus, Inc.
Chris Madden, Signal Integrity Engineer, Rambus, Inc.
Chuck Yuan, Signal Integrity Engineer, Rambus, Inc.
15.1: Abstract
15.2: Introduction
15.3: Power Supply Design Environment Requirements for Gigabit I/O Interfaces
15.4: Overview of Gigabit I/O Interface Test System
15.5: Measurement of Supply Noiseâ

winworm

这本书可以说集PI之大成，国际知名的PI专家轮番登场，全是工程派的高手。

yanhuaw

[em01]