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发表于 2008-10-8 15:59:00 | 显示全部楼层

OMG.........没见过这么称职的版主

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 楼主| 发表于 2008-10-15 08:42:00 | 显示全部楼层
Sisoft 2008.10 Release Notes:
Signal Integrity Software, Inc. is pleased to release Version 2008.10 of SiSoft software.
This document contains the release notes for this version of software.
Note: Starting with version 2008.04, all of SiSoft's products (Quantum-SI, SiViewer,
Quantum Channel Designer) are released together and installed via a common
installation program. See the Installation Guide for information on the new default install
path.


Enhancements in 2008.10:
• General Enhancements
o Ability to change text size in schematic editor from right-click menu
o New site configuration directory environment variable:
SISOFT_SITE_CONFIG_DIR
• QCD Enhancements
o State added to Channel Analysis Report
• SiViewer Enhancements
o Added ability to view solution space from waveform in QCD Results mode
o Node display in QCD Results mode shows Row ID and Tab in addition to
node name

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发表于 2008-10-28 11:58:00 | 显示全部楼层

支持下 没想到楼主还在持续更新啊

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发表于 2008-11-13 14:30:00 | 显示全部楼层
今年的IBIS大会,大家都show了winworm版主说的统计分析工具及其算法,这个时代来了。
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 楼主| 发表于 2008-11-14 12:16:00 | 显示全部楼层
对于这些Stateye工具,等我评估结束后,再跟大家详细说说。
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发表于 2008-11-17 12:43:00 | 显示全部楼层

楼主对今年的summit有何看法,以及对这个行业今后的发展和方向有何见解

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 楼主| 发表于 2008-11-25 08:54:00 | 显示全部楼层
最近很忙很忙,今年的ibis summit简短总结就是:没啥新东西,各个厂商独立山头,力推自己的解决方案,没有统一,高速仿真技术的推进速度放缓,多数用户继续观望,高速串行通道的仿真继续痛苦中。


另外有个消息就是CST 2009的发布:

Key new features in CST STUDIO SUITE 2009
 New and enhanced solver technology
 True transient 3D EM/circuit co-simulation using LINMIC technology with CST MWS
 Transient thermal solver to simulate the heating process
 Bio-heat equation for realistic modelling of physiological cooling
 Significant performance increase in Integral Equation solver, particularly for structures smaller than 20 wavelengths
 True Geometry Adaptation. The mesh adaptation of the tetrahedral frequency domain solver not only refines the mesh, but also snaps to the geometry
 High-end simulation
 64 bit frontend and MPI based parallelization for the handling of very large and complex structures
 User friendly
 User interface optimised for productivity
 Bend sheet operation for conformal modelling
 Improved user/modeller interaction
 New products for SI and EMC analysis
 CST PCB STUDIO™ and CST CABLE STUDIO™ are fully integrated in CST DESIGN
ENVIRONMENT™. Results can be used in CST MWS as field sources for further evaluation.
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 楼主| 发表于 2008-11-30 21:05:00 | 显示全部楼层
DesignCon2009要来了:

DesignCon 2009 Schedule
 
Monday, February 2
9:00 am - Noon    
TF-MA1 | Tutorial
Practical Techniques for Understanding, Modeling, and Efficiently Suppressing the Noise Coupling through Chip, Package, and PCB in Mixed-Signal Integrated Circuits and Systems-on-Chip
   
TF-MA2 | Tutorial
Signal Integrity Measurement Methods and Practices
   
TF-MA3 | Tutorial
Impact of Power Management Techniques on SoC Design and Verification
   
TF-MA4 | Tutorial
Fixturing and Calibration Techniques for Obtaining Wide Bandwidth Measured Data for Time Domain Simulations and Measurement-Based Modeling
   
TF-MA5 | Tutorial
Ensuring Functional Closure of a Multi-Core SoC Through Verification Planning, Implementation and Execution
Noon - 1:00    
Monday Keynote Luncheon
   
Mark Gogolewski
Speaker:
Mark Gogolewski
Chief Technology Officer, Engineering Department
Denali Software

Listen to podcast
1:30 pm - 4:30 pm    
TF-MP1 | Tutorial
CoReUse/QCore - Industries First Design Reuse Methodology with Compliance Checking Tool
   
TF-MP2 | Tutorial
Advances in Gigabit Channel Measurement-Based Characterization and Simulation
   
TF-MP3 | Tutorial
Design and Verification for High-Speed I/Os at Multiple to >10 Gbps with Jitter and Signal Integrity Optimization
   
TF-MP4 | Tutorial
Understanding Grounding Concepts in EM Simulators - What the Signal Integrity Engineer Needs to Know

   
TF-MP5 | Tutorial
Multicore and Virtualization Key Enablers for Next-Generation Network Architecture

4:45 pm - 6:00 pm    
Technical Panel
How Can Semiconductor Designers Meet High Performance/Low Power Requirements for Customers by Providing Greater Choice at Advanced Technology Nodes?

Chairperson:
Tom Quan
Deputy Director, Design Service Marketing
TSMC
   
Technical Panel
The Case of the Closing Eye - Addressing the Industry's Next-Gen Serial Data Design Validation Challenges
Loberg Chris
Chairperson:
Chris Loberg
Senior Manager, Business Instruments
Tektronix
   
Technical Panel
Power Distribution Planes: To Split or Not to Split?
Istvan Novak
Chairperson:
Istvan Novak
Distinguished Engineer, SPARC Volume Servers
Sun Microsystems
Tuesday, February 3
8:30 am - 9:10 am    
3-TA1
Achieve Higher Performance and Lower Power Consumption for Mass Storage Designs with SATA Device IP
   
6-TA1
Analysis of Crosstalk between Signals Routed over Discontinuous Reference Planes
   
7-TA1
Optimizing Connector Models for Signal Integrity Use
   
8-TA1
The Use of Optimization in Signal Integrity Performance Centric High-Speed Digital Design Flows
   
10-TA1
FPGA/ASIC Pre-Driver PDN SSN and Its Impact on SSJ
   
13-TA1
Active Cancellation of Noise Coupling in Mixed-Signal Integrated Circuits: Methodology, Design Examples, and Experimental Results
8:30 am - 10:00 am    
Business Forum Panel
Design This! New Strategies for New Devices
Chairperson:
Jason Isberg
Director, Asia Operations, Public Relations
Loomis Group

9:20 am - 10:00 am    
3-TA2
Configurable DAC for Mixed-Signal SoC Integration, with Maximum Design Reusability
   
6-TA2
Incorporating SSN Analysis in Constraint-Based System Design
   
7-TA2
Practical Analysis of Backplane Vias for 5 Gbps and Above
   
8-TA2
Quantifying Crosstalk-Induced Jitter in Multi-Lane Serial Data Systems
   
10-TA2
A Novel Methodology to Handle the Layout Constraints for Designing an Optimal Power Delivery Network
   
13-TA2
Fully Analytical Methodology for Fast End-to-End Link Analysis on Complex Printed Circuit Boards including Signal and Power Integrity Effects
   
14-TA2
Web2.0 Tools for Engineers
10:15 am - 10:55 am    
2-TA3
Verification of High-Speed SerDes Designs Using an EDA-Based Silicon-Accurate Behavioral Modeling and Simulation Methodology
   
3-TA3
Intellectual Property - Fraud Protection
   
4-TA3
Worst-Case Switching Pattern for Core Noise Analysis
   
7-TA3
Performance Calibration of High-Speed Serial Links
   
8-TA3
Analysis of Random Noise and the Effect of Band-Limited Noise on Stressed-Eye Receiver Tolerance Tests
   
10-TA3
Maximizing Performance of System-Level Decoupling Solutions by Decoupling Capacitor Selection and Placement Analysis and Verification
   
13-TA3
De-Embed Probe with New Switched Load Tip Technology
10:15 am - 11:45 am    
Business Forum Panel
Embracing a New Paradigm: EDA Tools and IP as Solutions Enablers
Bill Martin
Chairperson:
Bill Martin
Chairman
Global Semiconductor Alliance GSA
General Manager, Verification IP
Mentor Graphics
11:05 am - 11:45 am    
2-TA4
Multivariate Multi-Objective Analog Design Optimization Using High-Level Analog Testbenches
   
3-TA4
Toward Harnessing the True Potential of IP Reuse
   
4-TA4
System IO Planning and Design Feasibility - Challenges and Solutions
   
7-TA4
A Signal Integrity Comparison of 25 Gbps Backplane Systems Using Varying High-Density Connector Performance Levels
   
8-TA4
A New Physical Mechanism-Based Jitter Classification Method and Its Applications
   
10-TA4
Power-Gating Design Tradeoffs and Considerations for Production Low-Power Designs
   
13-TA4
Verify Your Signal Integrity Margins: De-Embedding of Fixtures and Probing in a Real-Time Digital Oscilloscope
Noon - 12:30 pm    
Tuesday Keynote Address
Wally Rhines
Speaker:
Wally Rhines
Chairman and Chief Executive Officer
Mentor Graphics
12:30 pm - 6:30 pm    
Technology Exhibition
12:30 pm - 2:00 pm    
Lunch Served on the Exhibit Floor
12:45 pm - 2:00 pm    
University Program
Design Challenges for Next-Generation, High-Speed Ethernet: 40 and 100 GbE
seamus crehan
Moderator:
Seamus Crehan
Vice President
Dell 'Oro
2:00 pm - 2:40 pm    
1-TP1
A Case Study: Critical Area and Critical Feature Analysis of Production 90nm Designs at LSI Corporation
   
3-TP1
C++ IP Design and Reuse
   
5-TP1
Common Mode Effects on Multi-Gigabit-Per-Second Interconnects
   
6-TP1
Analyzing Signal and Power Integrity Limitations for Mobile Memory Systems in PoP Environments
   
8-TP1
Comparison of BER Estimation Methods That Account for Crosstalk
   
11-TP1
The Application of High-Speed Serial Interfaces to Highly Sensitive EMI Applications
   
12-TP1
Guidelines for Multiport and Mixed-Mode S-Parameter Measurements in High-Speed Interconnection Design
2:00 pm - 3:30 pm    
Business Forum Panel
Collaboration across the Changing Design Chain
Dian Yang
Chairperson:
Dian Yang
Senior Vice President, Product Management
Apache Design Solutions
2:50 pm - 3:30 pm    
1-TP2
Equation-Based DRC: A Novel Approach to Resolving Complex nm Design Issues
   
3-TP2
Skeleton, an Approach to Maximize Reuse across Multiple Product Families
   
5-TP2
A Simple Via Experiment
   
7-TP2
Virtual Compliance Design Kit, Including Optimization and Sensitivity Analysis for Serial RapidIO up to 6.25 Gbps
   
8-TP2
Noise and Jitter Analysis for PLL-Based Frequency Synthesizer
   
11-TP2
Control of Electromagnetic Radiation from Integrated Circuit Heat Sinks
   
12-TP2
Contactless Vector Network Analysis - A New Approach for S-Parameter Measurements
3:45 pm - 5:00 pm    
Technical Panel
Selecting IP in a Complex Design Environment

Chairperson:
Raghavan Menon
Director of Engineering, ASIP
Virage Logic
     
Technical Panel
Multi-Die Chip/Package Co-Design for SiP Applications

Chairperson:
An-Yu Kuo
Chief Architect
Apache Design Solutions
     
Technical Panel
High-Speed Channel Designs - Challenges and Solutions

Chairperson:
Moises Cases
Distinguished Engineer, STG
IBM
   
Business Forum Panel
New Media/New Marketing: Using On-Line Media to Gain a Competitive Edge

Chairperson:
Rhonda McGee
Director of Research, Boston
Reed Business Information
5:00 pm - 6:30 pm    
Exhibits and Reception
Wednesday, February 4
8:30 am - 9:10 am    
1-WA1
A Self-Adaptable Slew Rate Control, Variable Power Supply Output Buffer for Embedded Microcontroller Applications with EMI Improvement Using Geometric-Load-Slew Factor Approach
   
4-WA1
Feasibility of Multi-Gigabit Memory Interface in LQFP Packages
   
6-WA1
A Study of Transmission Technology to Support 25 Gbps Serial Signaling for Parallel Architectures in Multi-Board Coplanar PCB Systems
   
7-WA1
Crosstalk in High-Speed Via Pin Fields, Including the Impact of Power Distribution Structures
   
10-WA1
Prediction and Measurement of Supply Noise Induced Jitter in High-Speed I/O Interfaces
   
12-WA1
Measurement-Assisted Electromagnetic Extraction of Interconnect Parameters on Low-Cost FR-4 Boards for 6-20 Gbps Applications
   
13-WA1
Crosstalk Amplification by Resonance
   
14-WA1
Modeling Design Services for Improving Service Delivery Effectiveness
9:20 am - 10:00 am    
1-WA2
Design Space Exploration for High-Performance Signal-Processing Hardware Using ESL Design Methodology
   
4-WA2
Broadband Methodology for Power Distribution System Analysis of Chip, Package, and Board for High-Speed IO Design
   
6-WA2
Clock Jitter Reduction in High-Speed Interfaces
   
7-WA2
Methodology of Characterizing Chip-to-Chip Serial Interconnects with AC Coupling Capacitors
   
9-WA2
Statistical Analog Front End and Decision Feedback Equalization
   
12-WA2
VNA Characterization of Cable Assemblies for Supercomputer Applications
   
13-WA2
40 Gbps Pre-Emphasized Serializer, Equalizer, and CDR CMOS Circuit Design with Full Channel Simulation
   
14-WA2
Business Considerations for Systems with RAM-Based FPGA Configuration
10:15 am - 10:55 am    
1-WA3
Analog Chip-Level Behavioral Modeling Using SVM Kernel-Based Data-Mining Techniques
   
4-WA3
Design Optimization of High-Speed Digital Systems
   
5-WA3
Bounding the Glass Weave Effect through Simulation
   
7-WA3
How Long Is too Long? A Via Stub Electrical Performance Study
   
9-WA3
Pseudo-Differential Vector Signaling for Noise Reduction in Single-Ended Signaling Systems
   
10-WA3
Examining the impact of split planes on signal and power integrity
   
12-WA3
Characterizing Non-Standard Impedance Channels with 50 Ohm Instruments
10:15 am - 11:45 am    
Business Forum Panel
Unifying Design Processes to Enhance Productivity

Chairperson:
Lawrence Romine
Business Development Manager, Sales and Marketing
Altium
11:05 am - 11:45 am    
1-WA4
Method and Apparatus of Continuous PLL Adaptation to Variable Reference Input Frequency
   
4-WA4
Time and Frequency Analysis of Signal Noise as a Function of Power Noise and Vice Versa of a Microcontroller (µC) Plus Its Packaging (LQFP+PCB)
   
5-WA4
Power Integrity Effects of High-Density Interconnect (HDI)
   
7-WA4
BER Performances for High-Speed Serial Link System Estimated by Using Quasi-Analytical Method
   
9-WA4
New Methods of Measuring the Performance of Equalized Serial Data Links and Correlation of Performance Measures across the Design Flow, from Simulation to Measurement, and Final BER Tests
   
11-WA4
Common-Mode EMI from Disk Drive Gigabit Serial Interfaces
   
12-WA4
Application of Launch Point Extrapolation Technique to Measure Characteristic Impedance of High-Frequency Cables with TDR
Noon - 12:30 pm    
Wednesday Keynote Address
Paolo Gargini

Speaker:
Paolo Gargini
Director, Technology Strategy
Intel Fellow, Technology and Manufacturing Group
Intel
12:30 pm - 6:30 pm    
Tehcnology Exhibition
12:30 pm - 2:00 pm    
Lunch and Exhibits
2:00 pm - 2:40 pm    
2-WP1
Formal Verification of Multi-Level Model System Using UPF
   
4-WP1
SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity
   
5-WP1
Achieving 100% PCB/Substrate Level ESD Protection to 30 KV Using VSDTM Nano-Composites
   
6-WP1
The Design and Signal Integrity Analysis of a TB/sec Memory System
   
9-WP1
Adaptive Transmit Equalization for Hybrid Optical-Electrical Links Operating at Speeds up to 17.0 GBd
   
10-WP1
An Efficient Time-Domain Method for the Analysis and Design of the Decoupling Networks in High-Speed Printed Circuit Boards
   
12-WP1
Platform Validation using Intel® IBIST
2:00 pm - 3:30 pm    
Business Forum Panel
Do It Right or Do It Over? Signal Integrity Engineer in the Era of Highly Compressed Project Schedules

Chairperson:
Colin Warwick
Product Manager, EEsof
Agilent Technologies
2:50 pm - 3:30 pm    
2-WP2
Using a Memory Access Pattern Test Suite to Predict System Performance
   
4-WP2
The Effects of Chip and Board Behavior on Package-Centric, System-Aware Power Delivery Design
   
5-WP2
Advances in Plating Technology
   
7-WP2
Interconnect Design Optimization and Characterization for Advanced High-Speed Backplane Channel Links
   
9-WP2
40/100 Gbps Transmission over Copper: Myths and Realities
   
11-WP2
EMI from Multi-Gigabit SerDes Differential Pairs
   
12-WP2
Characterizing Jitter Transfer in Clock Circuits
3:45 pm - 5:00 pm    
Technical Panel
Getting What You Pay for at 32 nm
joey sawicki

Chairperson:
Joseph Sawicki
Vice President and General Manager, Design-to-Silicon Division
Mentor Graphics
   
Technical Panel
Power-Aware Verification: Is It a Front-End or a Back-End Issue?

Chairperson:
Bhanu Kapoor
Consultant/Owner
Mimasic
   
Technical Panel
Measurements versus Simulations: Electrical Modeling at Future Data Rates and Physical Dimensions

Chairperson:
Brett Grossman
Senior Staff SI Engineer, Sort Test Technology Development
Intel
   
Business Forum Panel
Globalization of Product Engineering
Vasudevan Aghoramoorthy
Chairperson:
Vasudevan Aghoramoorthy
Vice President, Semiconductor and Systems,
Product Solutions
Wipro Technologies
5:00 pm - 6:30 pm    
Exhibits and Reception
Thursday, February 5
9:00 am - 9:40 am    
7-TH1
A Highly Effective 25 Gbps Backplane Channel Model
   
10-TH1
Voltage Regulator Module and Power Distribution Network Optimization
   
12-TH1
Characterization and Focus Calibration of ATE Systems for High-Speed Digital Applications
   
13-TH1
Utilizing Electronic Dispersion Compensation (EDC) and embedded waveform viewing technologies in next generation backplanes
9:50 am - 10:30 am    
7-TH2
New Serial Link Simulation Process, 6 Gbps SAS Case Study
   
10-TH2
PCB Power Delivery Optimizations for the Cost-Driven Era
   
12-TH2
A Comparison of Fixture Removal Methods for Characterization of Differential PCB Channels
   
13-TH2
Noise Injection for Design Analysis and Debugging
10:40 am - 11:20 am    
7-TH3
Development of USB3 Interconnects - Compatible Extension into Multi-Gigabit Bandwidth Performance
   
10-TH3
Switching Voltage Regulator Noise Coupling Analysis for Printed Circuit Board Systems
   
12-TH3
High-Performance and Cost-Effective Time-Domain TRL (t-TRL) Calibration Technique for High-Speed PWC Characterization and Qualification
   
13-TH3
Leveraging Probe De-Embedding Technique for Multi-Gigabit FPGA Package Characterization
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 楼主| 发表于 2008-12-30 08:58:00 | 显示全部楼层
2008年即将过去,忙碌的一年,多事的一年,期待一下2009吧!

2009将有2本si book出版,都是进阶版本:

Advanced Signal Integrity for High-Speed Digital Designs (Hardcover)
by Stephen H. Hall (Author), Howard L. Heck (Author)

这本书的出版日期一再延后,现在应该不会再跳票了吧,最初只有300多页,到现在膨胀到600多页,将近翻倍,这也从另一个侧面说明si发展迅速,以至于book的内容更新还跟不上,新的内容集中在后半部分,主要是关于高速串行互连设计的,而我想看到的也正是这部分。

Editorial Reviews
Product Description
Signal integrity has become the key issue in most high-performance digital designs. Now, from the foremost experts in the field, this book leverages theory and techniques from non-related fields such as applied physics, communications, and microwave engineering and applies them to the field of high-speed digital design. This approach creates an optimal combination of theory and practice that is meaningful to practicing engineers and graduate students alike.
Product Details

    * Hardcover: 682 pages
    * Publisher: Wiley-IEEE Press (March 23, 2009)
    * Language: English
    * ISBN-10: 0470192356
    * ISBN-13: 978-0470192351

Stephen Hall, Intel Corporation
    
Stephen Hall began his career in 1992 in the Special Purpose Processor Division of the Mayo Foundation developing multi-gigabit modeling techniques for X-band digital radar and serial optical links. In 1996, Stephen accepted a job at Intel, where he was lead designer for buses on Pentium? II, III, and IV systems, coordinated research with universities, led research teams in the area of high-speed modeling, and taught Signal Integrity courses. In 2000, Stephen published the textbook "High-Speed Digital System Design" through John Wiley & Sons and is currently co-authoring a new book, "Advanced Signal Integrity for High-Speed Digital Designs," which will be published in the fall of 2008. From 2003 to 2007, Stephen primarily researched new modeling and measurement solutions for channel speeds as high as 30 Gigabits per second and is currently leading PCIe3 channel development at Intel.     
Howard Heck, Intel Corporation    
Since joining Intel in 1995, Howard has held R&D engineering and management positions for system electrical technologies (interconnect, power, EMI). He led the development team for the Pentium? II 100 MHz Host Bus, earning an Intel Achievement Award, and managed teams that defined and delivered technology solutions for Direct RDRAM?, DDR II, Pentium? 4 Processor Host Bus, and Accelerated Graphics Port (AGP) interfaces. Prior to joining DEG, he led the Advanced Signaling Technologies team in Intel's Systems Technology Lab, focusing on modeling, simulation, measurement, and technology solution development for 10+ Gb/s signaling. He currently leads the signal integrity effort for Larrabee and Larrabee II. Howard earned the B.S.Ch.E. degree from Northwestern University in 1985, and the M.S.E.E. degree from the National Technological University in 1994. From 1985-1995 he was employed by IBM's printed circuit board manufacturing and high-performance packaging lab, where he led electrical development of their HyperBGA? packaging technology. Since 1997, Howard has also held a position as an Adjunct Professor at the Oregon Graduate Institute, where he teaches High-Speed Digital Interconnect Design. He has presented papers at several industry conferences, holds six patents with four pending, and is a Senior Member of the IEEE.

Preface.

Acknowledgments.

Chapter 1: Introduction: The importance of signal integrity.

1.1 Computing Power: Past and Future.

1.2 The problem.

1.3 The Basics.

1.4 A new realm of bus design.

1.5 Scope.

1.6 Summary.

1.7 References.

Chapter 2: Electromagnetic Fundamentals for Signal Integrity.

2.1 Introduction.

2.2 Maxwell’s Equations.

2.3 Common Vector Operators.

2.4 Wave Propagation.

2.5 Electrostatics.

2.6 Magnetostatics.

2.7 Power Flow and the Poynting Vector.

2.8 Reflections of Electromagnetic Waves.

2.9 References.

2.10 Problems.

Chapter 3: Ideal Transmission Line Fundamentals.

3.1 Transmission Line Structures.

3.2 Wave propagation on loss free transmission lines.

3.3 Transmission line properties.

3.4 Transmission line parameters for the loss free case.

3.5 Transmission line reflections.

3.6 Time domain Reflectometry.

3.7 References.

3.8 Problems.

Chapter 4: Crosstalk.

4.1 Mutual Inductance and Capacitance.

4.2 Coupled Wave Equations.

4.3 Coupled Line Analysis.

4.4 Modal Analysis.

4.5 Crosstalk Minimization.

4.6 Summary.

4.7 References.

4.8 Problems.

Chapter 5: Non-ideal conductor models for transmission lines.

5.1 Signals propagating in an unbounded conductive media.

5.2 Classic conductor model for transmission lines.

5.3 Surface Roughness.

5.4 Transmission line parameters with a non-ideal conductor.

5.5 Problems.

Chapter 6: Electrical properties of dielectrics.

6.1 Polarization of dielectrics.

6.2 Classification of dielectric materials.

6.3 Frequency dependent dielectric behavior.

6.4 Properties of a physical dielectric model.

6.5 The fiber-weave effect.

6.6 Environmental variation in dielectric behavior.

6.7 Transmission line parameters for lossy dielectrics and realistic conductors.

6.8 References.

6.9 Problems.

Chapter 7: Differential signaling.

7.1 Removal of common mode noise.

7.2 Differential Crosstalk.

7.3 Virtual reference plane.

7.4 Propagation of Modal Voltages.

7.5 Common terminology.

7.6 Drawbacks of differential signaling.

7.7 References.

7.8 Problems.

Chapter 8: Mathematical Requirements of Physical Channels.

8.1 Frequency domain effects in time domain simulations.

8.2 Requirements for a physical Channel.

8.3 References.

8.4 Problems.

Chapter 9: Network Analysis for Digital Engineers.

9.1 High frequency voltage and current waves.

9.2 Network Theory.

9.3 Properties of Physical S-parameters.

9.4 References.

9.5 Problems.

Chapter 10: Topics in High-Speed Channel Modeling.

10.1 Creating a physical transmission line mode.

10.2 Non-Ideal Return Paths.

10.3 Vias.

10.4 References.

10.5 Problems.

Chapter 11: I/O Circuits and Models.

11.1 Introduction.

11.2 Push-Pull Transmitters.

11.3 CMOS Receivers.

11.4 ESD Protection Circuits.

11.5 On-Chip Termination.

11.6 Bergeron Diagrams.

11.7 Open Drain Transmitters.

11.8 Differential Current Mode Transmitters.

11.9 Low Swing/Differential Receivers.

11.10 IBIS Models.

11.11 Summary.

11.12 References.

11.13 Problems.

Chapter 12: Equalization.

12.1 Introduction.

12.2 Continuous Time Linear Equalizers.

12.3 Discrete Linear Equalizers.

12.4 Decision Feedback Equalization.

12.5 Summary.

12.6 References.

12.7 Problems.

Chapter 13: Modeling and Budgeting of Timing Jitter and Noise.

13.1 The Eye Diagram.

13.2 Bit Error Rate.

13.3 Jitter Sources and Budgets.

13.4 Noise Sources and Budgets.

13.5 Peak Distortion Analysis Methods.

13.6 Summary.

13.7 References.

13.8 Problems.

Chapter 14: System Analysis Using Response Surface Modeling.

14.1 Introduction.

14.2 Case Study: 10 Gb/s differential PCB interface.

14.3 RSM Construction by Least Squares Fitting.

14.4 Measures of Fit.

14.5 Significance Testing.

14.6 Confidence Intervals.

14.7 Sensitivity Analysis and Design Optimization.

14.8 Defect Rate Prediction Using Monte Carlo Simulation.

14.9 Additional RSM Considerations.

14.10 Summary.

14.11 References.

14.12 Problems.

Appendix A: Useful formulae, identities, units and constants.

Appendix B: 4-port Conversions between T and S-parameters.

Appendix C: Critical values of the F-statistic.

Appendix D: Critical values of the t-statistic..

Appendix E: Derivation of the internal inductance using the Hilbert Transform.









Signal and Power Integrity - Simplified (2nd Edition) (Prentice Hall PTR Signal Integrity Library) (Hardcover)

这本书加入了Eric这几年在PI上的研究成果,估计会有20%左右的新内容,基本上也能猜测到里面的内容,Eric倡导的PI设计方法简单、实用,到时候大家可以收藏一本。

Editorial Reviews
Product Description
The #1 guide to signal integrity, updated with all-new coverage of power integrity, high-speed serial links, and more. - Up-to-the-minute comprehensive guidance: everything engineers need to know to understand and design for signal integrity - Authored by world-renowned signal integrity trainer, educator, and columnist Eric Bogatin - Focuses on intuitive understanding, practical tools, and engineering discipline - not theoretical derivation or mathematical rigor Summary Today's marketplace demands faster devices and systems that deliver more functionality and longer life in smaller packaging. Signal Integrity - Simplified, Second Edition is the first book to bring together all the up-to-the-minute techniques designers need to overcome all of those challenges. Renowned expert Eric Bogatin thoroughly reviews the root causes of all four families of signal integrity problems, and shows how to design them out early in the design cycle. Drawing on his experience teaching 5,000+ engineers, he illuminates signal integrity, physical design, bandwidth, inductance, and impedance; presents practical tools for solving signal integrity problems; and offers specific design guidelines and solutions. In this edition, Bogatin adds extensive coverage of power integrity and high speed serial links: topics at the forefront of signal integrity design. Three new chapters address: " Designing power delivery networks to support high-speed signal processing " Using 4-Port S-parameters, the emerging standard for describing interconnects in high speed serial links " Working with today's measurement and simulation tools and technologies

About the Author
Eric Bogatin is President of Bogatin Enterprises, a top provider of signal integrity training and education. His web site, BeTheSignal.com, provides 100+ free publications and 50+ hours of streaming video lectures. Active in signal integrity and interconnect design for 26 years, he has taught 5,000+ engineers through public short courses, in-house short courses at companies such as LSI Logic, Intel, Cisco and IBM, and graduate-level courses as an Adjunct Professor at San Jose State and UC Berkeley Extension.
Product Details

    * Hardcover: 730 pages
    * Publisher: Prentice Hall PTR; 2 edition (June 8, 2009)
    * Language: English
    * ISBN-10: 0132349795
* ISBN-13: 978-0132349796

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