业界观察

Jane123

[em01][em01]

winworm

李老师的第二本译作已经出版，这本书的起点比较高，偏重基础理论，翻译的难度要高于Eric的书，究竟质量如何要等看到书了才知道。目前只有China-Pub上到货了，joyo、dangdang上还没货，估计等几天就有了。

http://www.china-pub.com/44074

数字信号完整性:互连、封装的建模与仿真
    
市场价 ：￥50.00
普通会员 ： ￥40.00
1-3星会员： ￥39.00
4-5星会员： ￥37.50(75折)
校园优惠价 ： ￥39.00

基本信息
【原 书 名】 Digital Signal Integrity: Modeling and Simulation With Interconnects and Packages
【原出版社】 Prentice Hall Press
【作　　者】(美)Brian Young [同作者作品] [作译者介绍]
【译　　者】 李玉山;蒋冬初[同译者作品]
【丛 书 名】 国际信息工程先进技术译丛.集成电路与半导体技术系列
【出 版 社】 机械工业出版社*     【书 号】 9787111253150
【出版日期】 2009 年1月 【开 本】 16开 【页 码】 363     【版 次】1-1
【所属分类】     通信 > 通信技术理论与基础
内容简介 目 录 作译者 封 面 查看评论(0) 勘误建议
【内容简介】
本书全面论述了数字系统及传输中的信号完整性问题；以数字系统为背景，在引入信令属性和互连模型的概念之后，介绍了反射、串扰、同时开关噪声等典型问题，以及互连线的多端口模型；以建模为主线，深入探讨了：电感、电容、电阻等无源元件模型，多引脚寄生参数的测量技术，互连的集总模型和宽带模型等。在提高篇讨论了端接、电源分布和先进封装等高级应用范例。.

本书对于从事数字信号完整性及电磁兼容技术的研究或设计开发人员来说，是一本难得又实用的工程参考书。...
【作译者介绍】

本书提供作译者介绍
Brian Young(杨·布赖恩)是摩托罗拉半导体部Somerset设计中心的技术部成员，从事PowerPCTM微处理器和RapidIOTM互连架构的封装互连以及I／O方面的设计。在七年多的时间里，他针对微处理器，快速静态RAM与DSP等，潜心研究高速信令的仿真、建模、测量及性能。他曾在得克萨斯 A&M大学(College Station)电气工程系任助教；在得克萨斯大学奥斯汀分校电气工程系任副教授。Dr．Young毕业于得克萨斯大学奥斯汀分校并获得博士学位；拥有六个与封装相关的专利；在国际会议和学术期刊上发表了大量论文。.... << 查看详细
【目录信息】

序言.
译者序
前言
第1章 数字系统与信令
1．1 提高性能时的折衷
1．2 信令标准和逻辑系列
1．3 互连
1．4 数字系统建模
第2章 信号完整性
2．1 传输线
2．2 理想点到点信令
2．3 非理想信令
2．4 不连续引起的突变
2．5 串扰
2．6 拓扑结构
2．7 同时开关噪声
2．8 系统时序
2．9 习题

chenjnh

[em01]

winworm

Sigrity 发布高速串行通道仿真工具Channel Designer，成为第三个支持AMI的EDA厂商。

早些时候，看到Cadence Channel Analysis tool的设计者Dr. Keshavan在2008年初从Cadence跳槽到Sigrity，我就在想Sigrity可能要搞高速串行通道的仿真，来分一杯羹，现在证实了我当初的想法，大家可以看看Sigrity Channel Designer的内核应该跟Cadence的差不多。Dr. Keshavan在Cadence还开发了SI/PI的仿真引擎tlsim。



http://www.sigrity.com/products/channeldesign/channeldesign.htm


Channel Designer addresses the challenges associated with high speed serial link designs. As speeds approach 10 gigabits a second and beyond, the need to assess bit error rate (BER) and overall channel performance is essential. Channel Designer includes a graphical schematic editor and comprehensive support of IBIS Algorithmic Modeling Interface (AMI) transmitter and receiver models. Channel templates are provided for on-chip algorithms as well as for board, package and connector physical structures. Unparalleled simulation accuracy is enabled by effective S-parameter handling. 2D and 3D eye diagrams and bathtub curves are useful in determining BER and confirming jitter tolerance.
    
pre / post layout electrical anaylysis; power and signal integrity     

Channel Designer Applications:
    
    Designing robust products that use multi-gigabit serial links (ex. PCIe, SATA, Xuai, Infiniband, USB)
    erforming assessments at every design stage from feasibility through verification
    Simulating with industry standard IBIS-AMI transmitter and receiver models
    Analyzing designs that consist of a single net through or an entire multi-board bus
    Identifying performance boundaries with automated sweeping of bus operating scenarios
    Determining BER with 2D and 3D eye diagrams and bathtub curves to ensure robust performance
    Confirming that equalization and clock data recovery enable desired data rates and physical layer implementations
    
pre / post layout electrical anaylysis; power and signal integrity     

Channel Designer Advantages:
    
    recise simulations for designs over broad frequency ranges (DC to 10+ gigahertz)
    roven S-parameter handling to ensure accurate system level time domain simulations
    Easy-to-use graphic channel capture including an novel net-based, block-wise schematic editor
    Unique support for cascaded IBIS-AMI models to simplify creation, debug and use
    Flexible and automated model hook-up with Sigrity's open Model Connection Protocol (MCP)
    Advanced crosstalk analysis to combat jitter in 10+ gigabit a second designs
    Short time to results with Sigrity provided generic Tx / Rx AMI models and channel templates
    Supports all popular PCB and package layout data formats



Channel Designer Press Release：

 Sigrity Unveils Breakthrough Channel Designer Solution
Advanced capabilities accelerate design of high-speed serial links

SANTA CLARA, Calif. - January 20, 2009 — Sigrity, Inc., the market leader in signal and power integrity solutions for ICs, packages and printed circuit boards, today announced Channel Designer™, an advanced analysis solution. It offers the flexibility and accuracy required for high-speed serial links, which have emerged as the communications backbone for modern design.

"Our customers have found that designs with high-speed serial links operating at multi-gigabit speeds require more than traditional analysis," said Dr. Jiayuan Fang, president of Sigrity. "It is essential to accurately predict bit error rate to ensure a robust implementation that can handle anticipated jitter and noise levels. With millions of bits of data to be considered over a wide frequency spectrum from DC to tens of gigahertz, it can be extremely challenging to obtain reliable time-domain simulation results from band-limited channel models. Channel Designer provides unparalleled precision, and builds on Sigrity's long-standing strength in S-parameter handling for accurate system-level transient simulation."


Channel Designer has many advanced features to help designers at every stage from feasibility studies through design verification. Its unique net-based block-wise schematic editor, pioneered by Sigrity, supports rapid design capture for a single net interconnect or a complete bus traversing multiple boards. Sigrity's Model Connection Protocol (MCP) automatically connects circuit models for each element of the channel identified in the schematic. Channel templates of board, package and connector structures are provided. Detailed models extracted from physical layout user databases are swapped in as designs progress. Channel Designer fully supports the IBIS Algorithmic Modeling Interface (AMI), which has emerged as the industry standard for transmitter and receiver modeling. AMI models now are available from leading IC vendors, and Sigrity provides a number of useful generic AMI-compatible transmitter and receiver models for early assessments of IO behavior. Sigrity's unique support for cascaded AMI models simplifies model creation, testing and use.

Channel Designer uses equalization and clock data recovery (CDR) modeling to anticipate the end-to-end behavior of serial links, and it rapidly simulates design alternatives. Advanced scenario sweep automation quickly identifies design boundaries.

Channel Designer also includes automated crosstalk analysis that specifically targets crosstalk-induced jitter and noise arising in links operating at more than 10 gigabits per second. Designers can quickly assess crosstalk from any number of sources, anywhere along the channel. The channel analysis output includes 2D and 3D eye diagrams, along with bathtub curves, for accurate bit error rate prediction.

Pricing and Availability

Channel Designer will be available on Windows and Linux platforms this quarter with pricing starting at $30,000.

winworm

IOMeth 将发布一个新品：SIMDE，主要是用于SI建模、校验等。

Signal Integrity Model Development Environment (SIMDE) is a powerful utility tool for SI model developers, testers and users. It integrates SI model building, checking, validating and testing functions together as well as a topology editor. It features Spice, IBIS, VHDL-AMS, Verilog-A(AMS) and many interconnect model formats.

winworm

IEC在2009年出版的一本新书：Signal Integrity Characterization Techniques

ISBN: 1-931695-93-8    ISBN: 978-1-931695930

Signal Integrity Characterization Techniques
Description: Signal Integrity Characterization Techniques addresses the gap between traditional digital and
microwave measurement technologies while focusing on a practical and intuitive understanding of
signal integrity effects within the data transmission channel. High-speed interconnects such as
connectors, PCBs, cables, IC packages, and backplanes are critical elements of differential channels
that must now be optimized using today’s most powerful analysis and characterization tools. Both
measurements and simulation must be done on the device under test and must yield data that
correlates with each other. Most of this book focuses on real-world applications of signal integrity
measurements—from backplane design challenges to advanced error correction techniques to jitter
measurement tools. The authors’ approach wisely address many of today’s high-speed
technologies, provides excellent insight into its future direction, and will teach the reader valuable
lessons pertaining to the signal integrity industry.

ABOUT THE AUTHORS
Mike Resso is a signal integrity application specialist in the component test division of Agilent
Technologies. He is responsible for the technical training of field engineers, symposium lecturing,
and the creation of sales tools that will expand the worldwide market growth of high bandwidth
oscilloscopes. His current activities include developing novel signal integrity measurement
techniques related to high-speed digital design applications, identifying new test methodologies in
the communications field, and interfacing with Agilent R&D engineers to bring innovative products
to the marketplace. He has over twenty years experience in the test and measurement industry,
and his background includes the design and development of electro-optic test instrumentation for
aerospace and commercial applications. His most recent activity has focused on the complete
multiport characterization of high speed digital interconnects using time domain reflectometry and
vector network analysis. He has authored over 20 technical papers in diverse fields such as infrared
detector probe systems, linearly variable optical filters, and electrically conductive antireflection
coatings. Mike received a B.S. degree in electrical and computer engineering from University of
California.
Eric Bogatin is signal integrity evangelist of Bogatin Enterprises, LLC which specializes in training
for signal integrity and interconnect design. His company offers a complete curriculum in short
courses and training materials to help accelerate engineers and managers up the learning curve to
be more effective in fields related to signal integrity. He has held senior engineering and
management positions at such companies as AT&T Bell Labs, Raychem Corporation, Advanced
Packaging Systems, and Sun Microsystems. For 20 years, he has been involved in various aspects
of signal integrity and inter-connect design, from the materials side, manufacturing, product
design, measurements and, most recently, education and consulting. Eric has written four books on
signal integrity and inter-connect design, over 200 papers, and most recently wrote a book entitled
Signal Integrity-Simplified published in 2004. Eric received his Ph.D. in physics from the University
of Arizona in Tucson in 1980 and his B.S. in physics from the Massachusetts Institute of Technology
in 1976.

Contents:
Part I: Getting Started – Introducing TDR and VNA Techniques and the Power of S-Parameters
Chapter 1: Signal-Port TDR, TDR/TDT, and Two-Port TDR: Interconnect Analysis is Simplified with
Physical Layer Tools
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies
1.1: Introduction
1.2: Single-Port TDR
1.3: Two-Port TDR/TDT
1.4: Two-Port TDR/Crosstalk
1.5: Two-Port Differential TDR (DTDR)
Chapter 2: 4-Port TDR/VNA/PLTS – Interconnect Analysis Is Simplified with Physical Layer Test
Tools
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies
2.1: Introduction
2.2: Four-Port Techniques
2.3: Summary
Chapter 3: Differential Impedance Design and Verification with Time Domain Reflectometry
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Product Manager, Lightwave Division, Agilent Technologies
3.1: Abstract
3.2: Overview
3.3: Summary
Chapter 4: Utilizing TDR and VNA Data to Develop Four-Port Frequency-Dependent Models
Jim Mayrand, Signal Integrity Consultant
Mike Resso, Product Manager, Signal Integrity Operation, Agilent Technologies
Dima Smolyansky, TDA Systems
4.1: Abstract
4.2: Signal Integrity Challenges
4.3: Trend to Differential Topologies
4.4: Model Extraction Methodologies
4.5: Typical Four-Port Measurement Systems
4.6: Understanding Four-Port Mixed-Mode Analysis
4.7: Differential Interconnect Analysis
4.8: Measurement Accuracy and Error Correction
4.9: Design Case Study: Silicon Pipe Channel Plane
4.10: Frequency and Time Domain Analysis
4.11: Partitioning the Impedance Profile
4.12: Correlating Measurements and Models
4.13: HSpice Subcircuit Model for Backplane Only
4.14: Discontinuities: Flush Connector versus Cable Break
4.15: HSpice Subcircuit Model for Backplane Flush Connector
4.16: Model Optimization Schematic: Cable and Connector
4.17: Analyzing Connector Shunt Loss
4.18: Analyzing Fringe Capacitance
4.19: Modeled S-Parameters from Simulated TDR Waveforms
4.20: Modeled Eye Diagram with and without Connectors
4.21: Conclusion
Chapter 5: Accuracies and Limitations of Time and Frequency Domain Analyses of Physical-Layer
Devices
Robert Schaefer, Technical Leader and R&D Project Manager, Signal Integrity Group, Agilent
Technologies
5.1: Introduction
5.2: Equipment Setup
5.3: Fundamental Differences between TDR and VNA Instruments
5.4: TDR and VNA Sources
5.5: Architectures and Sources of Error
5.6: Calibration and Normalization
5.7: Measurement Accuracies: Reciprocity, Repeatability, and Drift
5.8: Measurement Comparisons
5.9: Summary
Chapter 6: Data Mining 12-Port S-Parameters
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Signal Integrity Application Scientist, Component Test Division, Agilent Technologies
6.1: Abstract
6.2: High-Speed Serial Links and the Bandwidth of Interconnects
6.3: Four-Port S-Parameters
6.4: Twelve-Port S-Parameters and Information Overload
6.5: Serial-Link Performance Analysis
6.6: Losses
6.7: Impedance Continuities
6.8: Mode Conversion
6.9: Channel-to-Channel Crosstalk
6.10: Conclusion
Part II: Backplane Measurements and Analysis
Chapter 7: A Design of Experiments for Gigabit Serial Backplane Channels
Jack Carrel, System IO Specialist, Xilinx
Bill Dempsey, Owner and President, Redwire Enterprises
Mike Resso, Signal Integrity Application Scientist, Component Test Division, Agilent Technologies
7.1: Abstract
7.2: Introduction
7.3: Serial Backplane Channels
7.4: Backplane Platform Description
7.5: Daughtercard Description
7.6: Backplane Characterization
7.7: eHSD Connection Channels
7.8: HM-Zd Channels
7.9: HM-Zmm Channels
7.10: Crosstalk Measurements
7.11: Eye Diagram Analysis
7.12: Reference Channels
7.13: Summary
Chapter 8: Gigabit Backplane Design, Simulation, and Measurement: The Unabridged Story
Edward Sayre, Owner and Director, NESA
Jinhua Chen, Signal Integrity and EMI Engineer, NESA
Michael Baxter, Signal Integrity Engineer, NESA
Gautam Patel, Signal Integrity Engineer, New Product Development, Teradyne
John Goldie, Member of the Technical Staff, National Semiconductor
Mike Resso, Product Manager, Lightwave Division, Agilent Technologies
8.1: Introduction
8.2: Gigabit Backplane Design Case Study
8.3: Simulations
8.4: Measurements
8.5: Recommendations
8.6: Summary
Part III: Assuring Quality Measurements = Probing and De-Embedding
Chapter 9: The ABCs of De-Embedding
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies
9.1: Introduction
9.2: Why De-Embedding?
9.3: Principles of De-Embedding
9.4: Obtaining the S-Parameter of the Fixture
9.5: Direct Measurement of Fixture S-Parameters
9.6: Building the Fixture S-Parameter by Fitting a Model to Measurement Data
9.7: Simulating the Fixture S-Parameter with a 3D Field Solver
9.8: Summary
Chapter 10: Backplane Differential Channel Microprobe Characterization in Time and Frequency
Domains
Eric Bogatin, Chief Technologial Officer, GigaTest Labs
Mike Resso, Signal Integrity Operation, Agilent Technologies
10.1: Abstract
10.2: Differential Channels Will Proliferate
10.3: The Bottleneck of SMAs
10.4: Advantages of Microprobing
10.5: Design for Test
10.6: Physical Layer Characterization
10.7: Understanding Four-Port Mixed-Mode Analysis
10.8: Design Case Study: XAUI Backplane
10.9: Comparing Time Domain and Frequency Domain Data
10.10: Coupling Pulls Down Differential Impedence
10.11: Eye Diagram Simulation Using Four-Port S-Parameters
10.12: Non-Ideal Differential Signaling (AKA Mode Conversion)
10.13: Summary
Chapter 11: Differential PCB Structures Using Measured TRL Calibration and Simulated Structure
De-Embedding
Heidi Barnes, High-Frequency Device Interface Board Designer, Verigy, Inc.
Antonio Ciccomancini, Application Engineer, CST of America, Inc.
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies
Ming Tsai, Staff Hardware Development Engineer, Production Technology Division, Xilinx
11.1: Abstract
11.2: Introduction
11.3: Combined TRL Calibration and Simulated Structure De-Embedding for Multi-Mode N-Port
Systems
11.4: TRL Calibration Structures and Measurement Technique
11.5: Simulated Four-Port and 12-Port De-Embedding Structure
11.6: Device Structure under Test: Coupled and Un-Coupled via Pairs
11.7: Verification Using Four-Port Multimode TRL Calibration
11.8: Demonstration of the Combined TRL Calibration and Simulated Structure De-Embedding
Technique for Multi-Mode N-Port System
11.9: Summary and Conclusion
Chapter 12: Validating Transceiver FPGAs Using Advanced Calibration Techniques
Mike Resso, Business Development Manager, Signal Integrity Applications, Agilent Technologies
Hong Shi, Member of Technical Staff, Packing Technology, Altera
12.1: Abstract
12.2: Introduction
12.3: FPGA Applications Overview
12.4: Systematic Error Correction
12.5: Characterizing Differential Structures
12.6: Design Case Study
12.7: Conclusion
Chapter 13: Performance at the DUT: Techniques for Evaluating the Performance of an ATE System
at the DUT Socket
Heidi Barnes, Senior Application Consultant, Verigy
José Moreira, Senior Application Consultant, Verigy
Michael Comai, Senior Product Engineer, AMD
Abraham Islas, Senior Product Engineer, AMD
Francisco Tamayo-Broes, Product Development Engineer, AMD
Mike Resso, Signal Integrity Measurement Specialist, Component Test Division, Agilent
Technologies
Antonio Ciccomancini, Application Engineer, CST
Orlando Bell, Vice President, Engineering, GigaTest Labs
Ming Tsai, Principal Engineer, RF Design Group, Amalfi Semiconductor
13.1: Abstract
13.2: Introduction
13.3: Probing Technology, Interposer Design, and Mechanical Challenges
13.4: Calibration Techniques
13.5: Measuring the Probe and Probe Interposer Adapter
13.6: Test Fixture Performance Measurement
13.7: Focus Calibration on an ATE System: Measuring “at the DUT”
13.8: Conclusion
Chapter 14: Frequency Domain Calibration: A Practical Approach for the Serial Data Designer
Steven Corey, Principal Engineer, Electro-Optical Product Line, Tektronix
Eric Bogatin, President, Bogatin Enterprises
Dima Smolyansky, Product Marketing Manager, Tektronix
14.1: Abstract
14.2: Characterization of Serial Channels
14.3: Calibration Methods
14.4: Frequency Limits from Time Domain Measurements
14.5: Intrinsic Performance Limits
14.6: Variation in Typical Fixtures
14.7: Conclusion
Chapter 15: Practical Design and Implementation of Stripline TRL Calibration Fixtures for 10-Gigabit
Interconnect Analysis
Vince Duperron, Design Engineer, Molex
Dave Dunham, Electrical Engineer Manager, Molex
Mike Resso, Product Manager, Signal Integrity Applications, Agilent Technolgies
15.1: Abstract
15.2: Introduction
15.3: Why Calibrate?
15.4: Linear Two-Port Network Analyzer Measurements
15.5: VNA Measurement Errors
15.6: Vector Network Analyzer with Four Ports
15.7: A Real-World VNA Block Diagram Example: The Agilent N5230A-245
15.8: TRL Calibration Types
15.9: A Stripline TRL Fixture—A Design Case Study
15.10: The Macro Element View
15.11: Putting It Together
15.12: The Micro-Half of a TRL Design
15.13: Validation of TRL Fixtures
15.14: Using the Corrected Material Properties
15.15: Conclusion
Chapter 16: Channel Compliance Testing Utilizing Novel Statistical Eye Methodology
Anthony Sanders, Principal Engineer, Infineon
Mike Resso, Product Manager, Agilent Technologies
John D’Ambrosia, Manager, Semiconductor Relations, Tyco Electronics
16.1: Abstract
16.2: Introduction
16.3: StatEye Methodology
16.4: Cascading of Channel with Transmitter and Receiver Return Loss Model
16.5: Design Example Results
16.6: Conclusion
Chapter 17: Characterizing Jitter Performance on High-Speed Digital Devices Using Innovative
Sampling Technology
Osvaldo Buccafusca, Development Scientist, Lightwave Division, Agilent Technologies
Mike Resso, Product Manager, Agilent Technologies
17.1: Abstract
17.2: Introduction
17.3: Jitter Measurement
17.4: Random Sampling and Precision Time Base
17.5: Future Trends: Optical Sampling
17.6: Summary
Chapter 18: Signal Integrity Concerns When Modulating Laser Transmitters at Gigabit Rates
Stephen Reddy, Senior Design Engineer, Transmission Subsystems Group, JDS Uniphase
Laurie Taira, Senior Product Engineer, Research and Development, Delphi Connection Systems
Mike Resso, Product Manager, Lightwave Division, Agilent Technologies
Chapter 19: The Role of Dielectric Constant and Dissipation Factor Measurements in Multi-Gigabit
Systems
Eric Bogatin, President, Bogatin Enterprises
Shelley Begley, Team Leader, Agilent Technologies
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies
19.1: Abstract
19.2: Introduction
19.3: Dielectric Properties of Laminates
19.4: Impact of Dielectic Materials in Signal Integration
19.5: Measurement Methods
19.6: Split-Post Dielectic Resonator Method
19.7: Conclusion
Chapter 20: Designing Scalable 10G Backplane Interconnect Systems Utilizing Advanced
Verification Methodologies
Kevin Grundy, Chief Executive Officer, SiliconPipe
Haw-Jyh Liaw, Director, Systems Engineering, Aeluros
Gary Otonari, Engineering Project Manager, GigaTest Labs
Mike Resso, Business Development Manager, Signal Integrity Operation, Agilent Technologies
20.1: Abstract
20.2: Approach
20.3: Current Design Impediments and Approaches
20.4: AE1002 Equalization
20.5: Improving the Channel
20.6: Initial Functional Testing
20.7: Full System Analysis
20.8: Summary
Chapter 21: Investigating Microvia Technology for 10 Gbps and Higher Telecommunications
Systems
Mike Resso, Business Development Manager, Signal Integrity Applications, Agilent Technologies
Thomas Gneiting, Founder, AdMOS Advanced Modeling
Roland Mödinger, Senior Engineer, ERNI Electroapparate GmbH
Jason Roe, Application Engineer, ERNI Electroapparate GmbH
21.1: Abstract
21.2: Introduction
21.3: Telecom System Physical Layer Overview
21.4: Signal Integrity and Differential Signaling Backplane Data
21.5: Four Port Microvia Measurements
21.6: Microvia Construction
21.7: Modeling and Simulation Case Study
21.8: Summary and Conclusions
Chapter 22: ATE Interconnect Performance to 43 Gbps Using Advanced PCB Materials
Heidi Barnes, Senior Application Consultant, Verigy
José Moreira, Senior Application Consultant, Verigy
Tom McCarthy, Vice President, Taconic
William Burns, Senior Applications Engineer, Altanova Corporation
Crescencio Gutierrez, Engineering and Research and Development Manager, Harbor Electronics
Mike Resso, Signal Integrity Measurement Specialist, Agilent Technologies
22.1: Abstract
22.2: Introduction
22.3: Dielectic Materials for ATE Test Fixtures
22.4: The Taconic Fast-Rise Dielectic Materials
22.5: Experimental Results
22.6: Equalization to the Rescue
22.7: NEXT/FEXT Crosstalk Variations with PCB Materials
22.8: Dielectric Influence on Complex ATE Test-Fixture Stack-Up Decisions
22.9: Conclusion
Part VI: Future Directions
Chapter 23: Design and Test Challenges Facing Next-Generation 20 Gbps Interconnects
Jay Diepenbrock, Senior Technical Staff Member, Interconnect Qualification Engineering, IBM
Will Miller, Vice President, Engineering, Efficere Technologies
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies
23.2: The Need to Measure Signal Integrity
23.3: Signal Integrity Analysis
23.4: High-Performance Test Figures
23.5: Test Fixtures: A User’s Perspective
23.6: Conclusion
Author Biographies

winworm

除夕

马上就到牛年了，外面的此起彼伏的鞭炮声，又是一个不眠夜，回想起做SI的六年多时间，真是感慨万千，这个行当是越来越难做了，很多时候都会觉得自己像个小学生，难怪连牛顿都会说：我不知道世人的看法怎样，我只觉得自己好像是在海滨游戏的孩子，为一会儿找到一颗光滑的石子，一会儿找一个美丽的贝壳而高兴。

希望牛年是个好年头！

winworm

ADS 2009将在本月中旬正式发布，又是一次SI仿真功能的大提升：

Signal Integrity

    * Channel Simulator
    * New, fast eye diagram measurements
    * Djordjevic loss model for fast, causal multilayer models
    * Causality-corrected microstrip and stripline models
    * Threaded impulse characterization for faster convolution

Simulation

    * GPU enabled Transient simulator
    * Multi-threaded harmonic balance
    * Arbitrary Jitter Analysis with FrontPanel
    * Support HSPICE .pat statement
    * Improved Passive Circuit Design Guide
    * Wireless Libraries (WiMedia v1.2, 3GPP/ LTE MIMO v8.3.0 & v8.4.0)
    * Pole-zero voltage and current controlled sources

Physical Layout

    * DRC for Flattened Layout
    * DRC 3rd-party integration (Calibre, Assura, MailDRC)
    * PDK Builder for Schematic

Momentum G2

    * Improved meshing and resistance modeling
    * Port resequence utility
    * Substrate stack driven viewing utilities
    * New pre-/post-simulation 3D viewer (RFDE)
    * Graphical substrate editor import/export (RFDE)
    * Enhancements to BroadBand Spice Model Generator
    * Enhanced data transfer from Allegro

EMDS G2

    * 3D parameterized components
    * Fast frequency sweep for iterative solver
    * Symmetry planes

Usability

    * AEL Debugger
    * Data Display snap-to-grid for plot alignment
    * Per-job control on feature-bit bundle licenses
    * Improved ADS examples
    * New statistics and DOE tab for Variable Setup dialog

winworm

Eric Bogatin最近出版了一本科幻小说:Shadow Engineer

http://www.amazon.com/Shadow-Engineer-Eric-Bogatin/dp/1441414436


Consultant steers business into outer space
Signal integrity expert releases first sci-fi novel



Rick Merritt
EE Times
(01/26/2009 12:20 H EST)

SAN JOSE, Calif. — Tired of the drip, drip, drip of news about layoffs? Why not explore outer space?

That's what Eric Bogatin did. The veteran signal integrity consultant just released his first fiction book, a novel about a Silicon Valley engineer who winds up battling aliens on the moon.

"I've been a science fiction fan since I was eleven," said Bogatin, best known for his classes on topics such as crosstalk in 10 Gbit/second signaling. "About ten years ago I went through a period where I couldn't find any sci-fi books I wanted to read, so I decided I would write a book myself."

The result was "Shadow Engineer," released earlier this month and now available online.

"It's about a young Silicon Valley engineer who stumbles into a secret company with lots of high tech equipment including an experimental space craft," said Bogatin.

"They have made a secret discovery that relates to aliens who could harm the Earth. He works with an older math professor to figure out what the aliens want, and on the way he has to do battle with them in space and on the moon," he added.

In his real-life role as a consultant, Bogatin recently made his first visit to NASA's Johnson Space Center to teach a course.

"You drive through the front gate and it's like a trip back to your childhood when you looked to astronauts as your heroes--I had pictures of Mercury and Apollo astronauts on my wall," said the 50-something Bogatin. "It was emotionally a thrill to be in a place where history is made," he added.

He told the NASA engineers about his novel which was just about to be published at the time. "I met some engineers working on new space propulsion technologies, and I had to tell them some of the things I wrote about are not too far off from what they are working on," he said.

So far, Bogatin's sci-fi novel has only sold "about seven copies not to friends or relatives."

It is his fifth book. Bogatin's most recent text book, "Signal Integrity Simplified," was translated into Chinese and has sold well both in the U.S. and China. A second edition will be released this year.

The downturn is already impacting his business which is focused on classes conducted mainly around the U.S.

"The first thing that goes is training and the second thing that goes is travel, so we are trying something new with webinars," he said. "Overall, I hear the first quarter will be a dead one, and beyond that there's a lot of uncertainty," he said.

Meanwhile, Bogatin has mapped out a whole series of sci-fi books to follow his first novel. He also hopes to publish a set of his short stories. Bogatin hopes readers find the work a welcome distraction during the current recession.

"Maybe this will be a bit of a break for worrying about what will come down next week in layoffs and cutbacks," he said.

winworm

 Hyperlynx 8即将发布：

SAN FRANCISCO—Mentor Graphics Corp. Tuesday (Feb. 3) threw its hat in the ring of EDA vendors addressing power integrity in the printed circuit (pc) board space, rolling out HyperLynx PI.

HyperLynx PI (power integrity) is billed as easy-to-use and promises accurate analysis of power plane structures. The tool enables teams to design working power delivery systems while reducing design cycle times, prototypes and manufacturing re-spins, as well as product cost, according to Mentor (Wilsonville, Ore.).

David Wiens, a Mentor product marketing manager, acknowledged that some competitors have already offered power integrity tools for pc boards, but said Mentor's offering is more sophisticated and refined. He said the tool would benefit from tight integration with Mentor's established HyperLynx SI signal integrity tool, which Mentor claims owns 45 percent marketshare. The power integrity problem for pc boards is already served by vendors such as Ansoft, a subsidiary of Ansys LLC.

"It's one of those things where being first to market is not always best, especially in the space where there is a lot of education involved ," Wiens said. "We think we really have a differentiated solution that is going to take off like the SI tools did as well."

In fact, the power integrity space is close to what signal integrity was 10 to 15 years ago, when most engineers "just hoped it would work," rather than employ a specific methodology or tools, Wiens said. But this approach has disadvantages, he added, including the need for multiple re-spins on some designs, costing time and money. On the flip side, some products are over designed due to lack of information, costing resources as well, he said.

The intent of HyperLynx PI is to help design engineers who are being forced to make tough design trade-offs on power, Wiens said. Economics are forcing designers to eliminate unnecessary components, use cheaper components, reduce layer count and cut down on prototypes, he noted.

"Engineers want to innovate, but management is saying 'keep it under cost and deliver it on time,' " Wiens said. "You get these cost and design pressures and they work against an innovative engineer."

Avoiding over-conservative design
"We have advanced users today that are required to design over 30 power delivery structures into a single PCB, driven by the multiple voltage levels and power requirements of their high-performance ICs," said Henry Potts, vice president and general manager of Mentor's Systems Design division.

"The design of these structures requires quick and accurate analysis of both DC power drop and power noise," Potts said. "With accurate analysis, the power and ground plane structures and de-coupling capacitor number, as well as placements, can be determined, thus avoiding over-conservative design and higher product cost."

HyperLynx PI provides pre- and post-layout analysis of irregular power and ground plane structures incorporating the exact IC pin locations and models, according to Mentor. The results of the analysis can be both visual and textual, enabling the designer to quickly identify and resolve power and/or ground plane structure problems, the company said. HyperLynx also provides accurate analysis of the power integrity, enabling the designer to determine the best number, placement and values of de-coupling capacitors, Mentor said.

HyperLynx PI product is available now to select customers with pricing starting at $35,000, according to Mentor. General release is targeted for later this quarter, the company said. The product integrates with Mentor's Expedition, Enterprise, PADS and Board Station flows as well as third party pc board design solutions such as Allegro and CR 5000, Mentor said.

[此贴子已经被作者于2009-2-6 22:21:04编辑过]