MI知识扩展 --背板

sha_apr

这是自己翻译的一篇背板方面的英文。

High-Speed Backplanes Pose New Challenges to Comms Designers

高速背板给一般的设计者带来新的挑战

As backplane speeds move beyond 3 Gbit/s, designers will encounter problems not seen at lower rates. Fortunately, through the use of modeling techniques, designers can tackle these issues head on.

因为背板（的信号）运行速度在3 Gbit/s 以上，设计者将遇到（信号）在低速时见不到的问题。庆幸的是，设计者可以通过使用建模技术来处理遇到的麻烦。

The operating data rates of current state-of-the-art backplane serial links are in the 2.5- to 3.125-Gbit/s range. As silicon becomes available that can support higher data rates into the 5- and 10-Gbit/s range, comm system designers are looking for ways to support these higher rates within their existing backplanes.

目前（一些）背板(也) 用于最尖端的多链接（系统）。它的数据交换速度范围在2.5 – 3.125 Gbit/s的。随着硅（芯片）能支持高达5 – 10 Gbit/s 的数据交换速度，设计者们正在寻找方法来在他们现有的背板设计中也支持这样高的速度。

In the 5- to 10-Gbit/s range, the technical challenges created by phenomenon such as reflections and crosstalk increase. In addition, new voltage- and timing-related challenges have arisen that typically do not exist in lower data rate ranges. These include skin effect, dielectric loss, inter-symbol interference (ISI), and via stub effect.

在5-10 Gbit/s 的范围，由诸如反射和串扰等带来的技术挑战在增加。另外，一些新的，在原来的低交换速度下不存在的因素也开始浮出水面，比如与电压和时序相关的一些方面的事情。这些因素包括表面效应，介电损耗，信号间干扰，和导通孔的（多余的）尾端效应。

To overcome these challenges, system designers must develop accurate and efficient models for both the active and the passive components of the system. Silicon vendors also need channel models to successfully design proper on-chip circuits for implementing various techniques like equalization and reflection cancellation. By modeling the known deterministic effects of the channel, signal-integrity related problems can be understood, and techniques can be developed to minimize their impacts.

为了克服这些挑战，系统设计者一定要为系统中的主动元件和被动元件开发出精确的，有效的模型。硅（芯片）供应商也需要信道模型来成功的将线路和芯片设计成一体，以便应用各种各样的工艺技术，比如均等和发射消除技术。通过将已知的信道效果模块化，信号完整性方面的问题就易于理解，并且能够开发一些技术来将这些影响降至最低。

To develop a backplane model, individual models for connectors, packages, PCB traces and vias are needed. In this article, we'll examine the technical challenges that must be overcome to support 5- to 10-Gbit/s rates, and the corresponding channel model requirements.

开发一种背板模型需要独立的连接器模型，封装，线路板上的线路以及导通孔。在这篇文章中，我们将分析支持5-10 Gbit/s 速度所必需克服的技术挑战，以及相应的信道模型的要求。

sha_apr

Channel Impairments

（信息的）信道损害
As the data transfer rate on the channel increases, "old" problems are exacerbated, and "new" problems arise that must be addressed. Figure 1 shows the key timing and voltage related impairments that must be addressed as data rates increase.

随着数据传输速度的增加，“旧的”问题在恶化，而新的必须解决的问题在出现。图 1 显示了那些随着数据传输速度增加而出现的，必须解决的，主要的时序/电压相关的损害。 

Figure 1: Above 3 Gbit/s, backplane transmission becomes a major challenge.

图1:高于 3 Gbit/s, 背板的传输成为一个主要挑战.

[此贴子已经被作者于2009-2-23 15:21:42编辑过]

sha_apr

Figure 1 is divided into three regions of interest:

• The 100 Mbit/s to 1 Gbit/s region

• The 1 to 3 Gbit/s region

• The 3 to 10 Gbit/s region

图1被分成三个有趣的区间：

l        100 Mbit/s 到  1 Gbit /s 区间

l           1Gbit/s 到  3 Gbit /s 区间

l           3Gbit/s 到 10 Gbit /s 区间

The 100 -bit/s to 1-Git/s region is the better understood of the three. In this range the designer must compensate for the issues listed in the above drawing and remove fixed errors such as impedance mismatch and data/clock skew issues.

100-Mbit/s 到 1-Gbit/s 区间是在这三个中间比较容易理解的一个。在这个区间里设计者一定要对上面图1中列出来的问题进行补偿，对确定的误差要消除比如阻抗不匹配以及数据/时钟的相位差问题。

In the 1- to 3-Gbit/s range, the designer must make adjustments that are a function of the channel's electrical behavior, such as channel loss and distortion. These quantities are typically not known when the silicon is designed. Consequently, a feedback loop can be used to adjust the variables of concern. For example, the transmit driver output swing driving into a lossy channel can be adjusted by a feedback loop sensing the input swing at the far end receiver. The objective in this example is to overdrive the channel and compensate for its losses.

在1-3 Gbit/s 的区间内，设计者一定要对信道电子特性进行调整，比如信道损耗和失真。这些（要调整的电子特性种类的）数量在硅芯片设计时还是未知的。相应的，用一种循环反馈机制可以调整所担心的变量。例如，进入有损耗信道的传输驱动输出（信号）漂移可以用循环反馈机制来探知在遥远的输入端的漂移。在这个例子中的情况是用对信道进行过度驱动以及对它的损耗进行补偿。

Above 3 Gbit/s, the existing variables become harder to manage, and new variables begin to emerge as shown in the above drawing. These include skin effect, dielectric loss, intersymbol interference (ISI), via stub effect, ISI jitter, and inter-pair skew. Let's look at these six in more detail starting with skin effect.

在3Gbit/s以上的区间，对现存的变量管理变得很难，而且新的变量开始加入进来，就像上面图1中看到的。这些变量包括表皮效应，介电损耗，信号的码间干扰，导通孔的（多余的）尾端效应，信号编码间的干扰抖动，和差分对内的延迟差。我们来从表皮效应开始以更详细的角度看看这六个因素。

sha_apr

1. Skin Effect
Skin effect is a physical phenomenon related to high frequency transmission on a wire. At very high frequencies, the electromagnetic field of the wire causes most of the electrical current to become crowded at the edges of the wire. This phenomenon alters the distribution of the signal current throughout the wire and changes the effective resistance on the wire. The resulting effect is increased signal attenuation at higher frequencies.

1．表皮效应

表皮效应是和在导线上进行高频传输相关联的一种物理现象。在很高的频率时，导线的电磁场使得绝大多数电流集中在导线的边缘。这种现象改变了整个导线上的信号电流分布以及改变了导线上的有效电阻。这样一来就增加了信号在较高的频率下的信号损耗。

2. Dielectric Loss
There are a number of PCB dielectric materials on the market today. The amount of dielectric loss in the material greatly affects signal integrity at high speeds. The lower the amount of dielectric loss, the less negative impact on the signal.

2．介电损耗

在当今的市场上有相当数量的PCB绝缘材料。材料中的介电损耗在高速时会大大影响信号的完整性。介电损耗越少，对信号的负面影响就越少。

Figure 2 shows the total loss (conductor + dielectric) on a given trace at different speeds. The signal amplitude transfer function (output divided by input signal) is normalized at 1 where there is no attenuation in the channel.

图二显示了在固定导线的情况下，在不同传输速度下的总的损耗（导体 + 绝缘体）。信号的振幅传送函数（信号输出 / 信号输入）在1也就是信道中没有衰减的时候是正常的。

 

Figure 2: Loss as a function of frequency

 

图2：损耗和频率的函数关系

sha_apr

Between 1 and 100 MHz, the amount of conductor and dielectric loss is negligible. Throughout this range, the signal transfer function remains at about 1. At 1 GHz the signal has decreased to approximately 0.5, half of its original strength. At speeds above 5 GHz the signal strength drops below 0.2, losing approximately 80% of its original strength. Thus, losses are a major issue at these high frequencies.

在1-100 MHz导体和绝缘体的损耗可以忽略。在这一整个区域，信号的传送函数保持在1。在1GHz信号强度减少到大约0.5，原来的一半。在5GHz以上的速度时，信号的强度下降到0.2以下，损失了大约原来的80%。

Although FR4 is the most commonly used material, it clearly does not have the best electrical characteristics when measured in terms of dielectric loss, as shown in the Figure 5. Still, FR4 is generally preferred due to its lower production costs.

尽管FR4是用地最普遍的材料，当我们用介电损耗来衡量时，它本身很明显的不具备最好的电性能，参见图3（。尽管如此，FR4因为它的低生产成本，通常来说还是很理想的。

 

Figure 3: trace loss with FR-4 and Roger dielectrics

 

（图略同上）

图3: 布在FR-4和 Roger 绝缘体上的导体损耗

[此贴子已经被作者于2009-2-25 10:10:15编辑过]

sha_apr

3. Intersymbol Interference
ISI is a phenomenon caused by the different propagation velocities of low and high frequencies throughout a channel. The end result is a spreading of bits, also known as pulse spreading. Stated differently, transmitting a square pulse through such a channel results in a widening and flattening of the pulse at the far end. This implies that each data bit of information overlaps with its adjacent bits. This overlap can cause major distortions of the signal. At high data rates and in long channels, the ISI can be so bad that it becomes impossible to recognize an eye pattern on the oscilloscope. This is a major phenomenon limiting data transmission, and must generally be addressed starting at the 2 to 3 Gbit data rates in most system backplanes.

3．信道的（编）码间干扰(ISI)

ISI是一种物理现象，它是由整（一）个信道中的低频和高频的不同传输速率引起的。最终的结果是二进制位的扩展（a spreading of bits），也叫做脉冲展宽。另外一种描述是，在这样一个信道中传输一个方形脉冲将在远端得到一个宽一点的平坦一点的脉冲。这意味着每个信息数据位会与相邻的数据位发生交叠。这种交叠会导致信号的严重失真。在高的数据速率和长的信道下，ISI会害的在示波器上无法辨认眼图(译者注：一种像眼睛一样的图形，由不同的信号组成的，可以很容易在网上搜索到例子)。这是限制数据传输的一种主要现象，当大多数背板系统中的数据传输速率达到2-3Gbit时通常必须处理好它。

4. Via Stub Effect
At high frequencies, via stubs can cause reflections in the signal. These stubs are common on all PCBs, but at lower speeds their effects are negligible. The thicker the backplane traces, the larger the via stubs, which in turn causes the amount of signal reflections to increase. Ideally, the stub length, and resulting stub delay, should be kept as short as possible.

4．导通孔（多余的）尾端效应

在高频时，导通孔的多余尾端会导致信号的反射。这些尾端在所有的PCB中都普遍存在的，但是在低速时它们的影响可以忽略。背板越厚，导通孔的多余尾端越长，导致产生的信号反射也越多。理想的，导致尾端延迟的尾端长度越短越好。

5. ISI Jitter
ISI jitter is caused by intersymbol interference. Because the pulse's energy is seen to spread into the adjacent bits with ISI, this energy will combine with the previous and next bits respectively. The adding or subtracting of energy depends on the logical value of the current pulse, and the logical values of the previous and next bits. Since the amount of energy in each bit period varies as a result, the transition time between bits also varies. A movement in time of this transition time is called jitter. Therefore, bit-dependent jitter can result. This is known as ISI jitter.

5．ISI抖动

ISI抖动是由信号的码间干扰产生的。因为脉冲能量因为ISI而扩展到了相邻的数据位，所以这些能量就会和它之前的以及之后的数据位结合起来。能量的增加或者减少量取决于它目前的脉冲逻辑值，以及它之前的和之后的数据位的脉冲逻辑值。既然这样的结果是每个数据段的能量发生变化，那么数据段之间的传输时间也就不同了。这种传输时间上的时间移动被称为抖动。所以，由数据位而定的抖动就产生了。这就是熟知的ISI抖动。

sha_apr

6. Intra-pair skew
Intra-pair skew is the amount of skew between the two signals of a differential pair. This skew can be caused by variables such as a length mismatch between traces, non-uniform bends in the signal traces, via stubs, and via transitions.

6．差分对内延迟

差分对内延迟是指一对差分线之间的延迟数量。这种延迟可以由很多变量产生，比如线间的不匹配长度，信号线上不一致的弯曲，导通孔的多余尾端，以及导通孔跃迁（via transitions）.

Skew is normally measured as a percentage of the Unit Interval (UI). Even a slight amount of skew can dramatically impact the percentage of UI at high frequencies. For example, a 1% skew for a 30-inch trace correlates to a 5% UI mismatch at 1 Gbit/s and a 50% UI mismatch at 10 Gbit/s. This, in turn, reduces the data eye opening and increases the amount of jitter.

延迟通常以单位时间(UI: unit interval) 的百分比来衡量. 在高频时即使是很少数量的延迟也会戏剧性的影响到UI的百分比。比如，对于一段30-英寸长的线，1%的延迟会在1Gbit/s时引起5%的UI不匹配，会在10 Gbit/s时引起50%的UI不匹配。接着，它就会减小（眼图中）眼状开口大小，增加抖动量。

Equalization: Mitigating Impairments

均等化：减轻损害

Many of the channel impairments described above can be mitigated on-chip using equalization. This term is used to define circuits that can attenuate low frequencies and amplify high frequencies in either the transmit or receive directions, or both.

上面提到的信道损害可以在芯片上用均等化来减轻。这个术语用来界定这样的线路，它能削减低频和放大高频，可以是在发射端或者接收端，也可以在两端同时用。

In one form of receive equalization, the incoming signal is sampled at different delay points. At each delay point, the signal is multiplied by a predetermined coefficient value. Each of the resulting values are then summed together to effectively recreate the signal as if it had just left the transmitter, effectively negating the effects of the various channel impairments described above.

在一种接收均等化的情况下，进来的信号被在不同的延迟点来取样。在每一个延迟点，信号被用预先定义好的系数放大。每一个结果值跟着再组合在一起来，有效地再现（产生）信号，就像它刚离开发射器一样；有效地打消上面描述的各种信道损害的影响。

Receive equalization is typically performed using a digital or analog adaptive filtering method. The equalization circuit examines the filtered signal output and adjusts the coefficients to optimize the signal quality through a feedback loop.

典型的实现接收均等化是用数字自适应过滤的方法或者模拟自适应过滤的方法。均衡电路通过一种循环反馈机制来检查过滤的信号输出，调整系数来优化信号质量

sha_apr

In contrast to the receive equalizer, the transmit equalizer boosts the high frequencies of a signal by a fixed amount before it is sent out. In theory, the negative effects of the previously mentioned variables will occur on the boosted portion of the signal, thereby allowing the overall signal quality at the receiver to more closely resemble that which was sent out by the transmitter. In other words, the transmitter pre-distorts the signal in the opposite way from that created in the channel so that a better quality signal can be seen at the receiver.

和接收均衡器相反，发射均衡器在信号发射之前用一个固定增量来推动高频信号。在理论上，之前提到的变量的负作用将产生在信号的推进增量部分，所以使得接收端总体上信号的质量更加接近发射端。换句话说，发射器预先对信号作了一个反向变形所以在接收器上可以得到更好质量的信号。

In both the transmit and receive path, there are two ways to set equalizer coefficients. The first is manual equalization. Also known as "set and forget", this coefficient setting technique is based on manual channel measurements. It can also be calculated on the basis of a single-bit-response (SBR) test through the channel.

在发射和接收过程中，由两种方法来设定均衡器的系数。第一种是手动均衡化。也称作“一次性设置”，这种系数设定技术是根据手动信道测量。它也可以用基于信道的单数位反馈（SBR）测试来计算。

The second method is to use an adaptive equalization approach. By using an adaptive algorithm such as Least Mean Square (LMS), the equalizer can optimize the signal quality by modifying the coefficients on a continuous basis. This allows the equalizer to adapt to changing conditions in the back-plane. A continuously adaptive method is far superior than the "set and forget" method because it adjusts to the changing environment automatically. This is relevant because environmental effects such as temperature and humidity changes can have a dramatic impact on the channel behavior.

第二中方法是采用自适应均衡器的途径。通过用自适应运算法则比如最小平均数平方(LMS), 均衡器能通过连续改变系数来优化信号质量。这使得均衡器能适应底板上的情形变更。连续的自适应的方法远比一次性设定出众，因为它能根据变化的环境自动调整。这也相关是因为环境方面诸如温湿度的变化会给信道的性能带来戏剧性的影响。

sha_apr

System Modeling
Each of the points discussed above indicates an electrical variable that can impact signal integrity over the backplane. To effectively manage the negative effects at each of these points, the physical structures impacting these electrical variables should be modeled. Once each physical structure is modeled (package, trace, via, etc.) an overall system model can be developed that is representative of the point-to-point trace from device to device.

系统模型

上面讨论的每一点对应一种能影响背板上信号完整性的电变量。为了有效的管理每一项的负作用，影响这些电变量的物理结构应当模块化。一旦每个物理结构都模块化了（封装，线路，导通孔，等），一个总体的系统模块也就可以开发出来的，它代表着点到点线到线装置到装置（device to device）

Figure 4 shows a flow chart of the modeling process.

图4 显示了模块化的流程图 

Figure 4: System model flow chart.
 

图4：系统模型流程图

[此贴子已经被作者于2009-2-25 10:13:00编辑过]

sha_apr

The flow chart shown in Figure 4 includes test structures, 2D/3D simulations, a channel model, a system model, test chips, and system simulations. Let's look at each block in more detail.

图4的流程图包括测试结构化，2D/3D仿真，信道模块，系统模型，测试芯片和系统仿真。我们下面在更详细的程度上看看每一块。

1. Test Structures
The test structures include measurements that have been made at the various points in the signal path. These include package-to-board via, line card trace, line card via, backplane connector, backplane via, and backplane trace.

1．测试结构化

测试结构化包括在信号传输路线上不同点的测量结果。这些包括封装到板子的导通孔，线路卡上的线，线路卡上的导通孔，背板上的连接器，背板上得到通孔，和背板上的线。

Physical measurements are made on the electrical characteristics of each variable. Data from these measurements are then used to construct the overall channel model.

物理测量结果是对每个变量的电的特性而言。这些测量结果会用来建立总的信道模型。

2. 2D and 3D Simulations
Another way to develop component models is via 2- or 3-dimensional simulation. In this case the simulator takes the size, length, thickness, and other relevant physical parameters and calculates the relative electrical characteristics for that component. These two types of models are then used to build the channel model shown in Figure 4.

2．2D/3D仿真。

另一个方法来开发元件模型是通过2维或者3维仿真。在这种情况下，仿真器用元件的大小，长度，厚度，和其它相关联的物理参数来计算相关的电的特性。这两种模型跟着用来建立图4中的信道模型。

3. Channel Model
The channel model includes everything except the silicon devices on each end. The channel model is built and tested and the results are compared against a measured channel response to determine whether the model is working correctly. Based on this correlation, the channel model is modified to match the results of the physical measurements. The goal is to have an accurate channel model at the frequencies of interest such that it can be used reliably as a predictor of behavior when simulating the entire system.

3．信道模型

信道模型包括除了每个装置（device）末端的硅芯片外的所有东西。信道模型建好测试后，结果要和一个标准信道的结果相比较从而来界定模型是否工作正常。根据这个关联结果，来改变信道模型以和物理测量结果相吻合。目标是得到一个在所关心的频率下的精确信道模型，从而它可以用来在整个系统的仿真过程中作为一个可靠的探测器。