MI知识扩展 --背板

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4. System model and Active Signal Integrity Techniques
The system model includes not only the channel model, but also the silicon devices at each end. At data rates below 1 Gbit/s, the system model and the channel model should indicate in most cases that the signal degradation can be addressed using standard fixed or feedback techniques, as discussed earlier. Above 1 Gbit/s, additional signal integrity (SI) techniques must be employed to maintain overall signal quality.

4．系统模型和主动信号完整性技术

系统模型不仅包括信道模型还包括每个结尾的硅芯片。在数据速率低于1 Gbit/s时，系统模型和信道模型在绝大多数情况下应该显示出可以用标准固定的或者反馈的技术来解决的信号衰减，就像之前讨论的那样。在1 Gbit/s以上，附加的信号完整性技术一定要用到以保持整个的信号质量。

Active SI, or equalization, is required if the channel model simulation output dictates that additional steps must be taken to eliminate signal degradation. This is often the case above 1 Gbit/s, and generally always required in most systems above 3 Gbit/s.

主动SI(信号完整性)，或者均等化，在这种情况下是必需的 – 如果信道模型仿真的输出显示为了消除信号衰减一定要采取附加的步骤的话。这在1 Gbit/s以上比较常见，而在要求3 Gbit/s的觉大多说系统中则是经常见到。

5. Test chips and System Measurements
Once the active SI algorithm and circuit has been developed, test chips can be built to demonstrate that the equalization algorithms are working properly. System measurements can be taken on the test chip and on the overall system to ensure signal integrity from chip-to-chip. These results are then correlated to the system model to ensure the accuracy of the models.

5．测试芯片和系统测量

一旦开发出了主动信号完整性的算法和线路，就可以建造测试芯片来示范均等化算法是否工作正常。系统测量可以基于测试芯片也可以基于整个系统从而确保从芯片到芯片的信号完整性。

[此贴子已经被作者于2009-2-23 15:33:48编辑过]

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6. System Simulations
With a well-correlated and stable system model, the overall system simulation can be done. The system simulation takes into account other variables such as:

• Size of the channels in the chassis Number of potential cards

• Shortest distance over the backplane from card-to-card

• Longest distance over the backplane from card-to-card

6．系统仿真

用一个好相关性的稳定的系统模型，整个系统的仿真就可以做了。

系统仿真要考虑到其它的变量，比如：

• 底盘上的信道尺寸（size of the channels in the chassis）, 可能用道德板卡的数量

• 整个背板上从板卡到板卡的最短距离

• 整个背板上从板卡到板卡的最长距离

Using this information, the system simulator can interpolate the electrical characteristics for all other points in the chassis. For example, if the electrical characteristics between two points are measured, with the shortest distance being two inches and the longest distance being 10 inches, the system simulator can be used to calculate the electrical characteristics for all other points in between, provided a good system model has been built.

用这些信息，系统仿真器就能更改底盘上的其它点的电性能。比如，已知最短距离是2英寸和最长距离是10英寸，如果测量到了两点之间的电性能，系统仿真器就可以用来计算这个区域内所有其它的电，当然这是在好的系统模型已经建立好了的情况下。

Wrap Up

总结

The backplane is a complex system containing a number of variables that can impact signal integrity. The overall number of variables to be managed and the negative impact they have on signal quality increases with speed. At speeds over 3 Gbps, not only are the negative impact of existing variables increased, but new variables such as skin effect, dielectric loss, ISI, and via stub effect, must be taken into account.

背板是一个复杂的系统。它包括了一定数量的影响到信号完整性的变量。总的要管理的和对信号质量有负面影响的变量数量随着速率的增加而增加。在3 Gbps以上，不单止目前存在的变量的负面影响再增加， 新的变量比如表皮效应，介电损耗，ISI（信号的码间干扰），和导通孔（多余的）尾端效应，一定要考虑进来。

The addition of physical components within a given point-to-point link also causes signal degradation. These include PCB traces, connectors, via stubs, and the actual silicon devices themselves. Each time another impairment is factored in, signal quality is reduced at high frequencies.

在一个给定的点到点的连接中，额外的物理元件也会导致信号的衰减。这些包括ＰＣＢ线路，连接器，导通孔（多余的）尾端，和实际的硅装置本身。每次其它的损害被确认为信号质量的完整。

To overcome these challenges, system vendors must develop accurate and well-correlated models for both the active and the passive components of the system. Silicon vendors need quality channel models to successfully design proper on-chip circuits for implementing various techniques like equalization and reflection cancellation. By modeling all the known deterministic effects of the channel, signal-integrity related problems can be well understood and minimized.

为了克服这些挑战，系统供应商一定要开发精确的和关联很好的模型，不管是系统上的主动元件或者是被动元件。硅芯片供应商需要高质量的信道模型来成芯片级的设计，从而来用不同的技术，比如均等化和反射消除。通过将所有已知的有确定原因的信道因素模块化，和信号完整性相关的难题就能被很好的理解和最少化。

[此贴子已经被作者于2009-2-25 13:49:03编辑过]

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About the Author

关于作者：

 
Jean-Marc Patenaude is a technical marketing director in Rambus' Logic Interface Division. He holds a Bachelor of Science degree in electrical engineering from the University of Waterloo and a Master of Science degree in electronics from Carleton University. Jean-Marc can be reached at jmp@rambus.com

Jean-Marc Patenaude 是一位Rambus逻辑界面分部的市场技术总监。他获得了Waterloo大学电子工程学科的学士学位，Carleton大学的电子博士学位。他的邮件地址是jmp@rambus.com

[此贴子已经被作者于2009-2-25 10:05:51编辑过]

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完了。

sha_apr

图3和图4 已经更新。

FPC-SM

太专业了，要顶的。

funmy

看一下，还是不懂，实在太专业了！

scz2007

太精彩了，但看不懂，呵呵，还是要顶一下哟

 

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色斑斓

牛,一定要顶!!!!!!!!!!!

lizmfk725

看不懂，实在太专业了！