关于高速差分串行信号设计的问题

alansandy0923

邵老师：
   您好！！
            您在书7.3中提到可以在xilinx下载Xilinx MGT Kit 套件，但我翻边了xilinx的网站也没找到，老师能否提供下，我的邮箱：caoxiaohua0923@126.com,谢谢老师。
            在没找到xilinx的套件下，我在altera中找到了一个套件，基于hspice模型的，但我仿真就是报错，
是否是我的设置有问题，（我已按照Hspice2010）

点simulate后，跳出hspice文本窗口，我导入SP文件后，sigxplore就一直卡在那里，最后啥东西也没出来，
见下图：

老师，是不是我的spice有错误，还是cadence没破解完全啊
hspice文本中的部分信息入下图：（是不是路径设置问题，我的套件包在D盘里，不在C盘）


期待邵老师的答复！！！！谢谢！！！！
最后SQ信息栏显示信息为：
Using SigNoise run directory 'D:/Cadence Project/Cadence_SIIGX_Kit_0p3/Simulation/Hspice_Verify/sigxp.run'
Reading report definition file 'D:/Cadence/SPB_16.2/share/pcb/signal/reports.dat'.
Finished reading report definition file successfully.
Standard report 'ComprehensiveForSourceSyncBus' has been replaced.
Reading report definition file 'D:/Cadence/SPB_16.2/share/pcb/signal/custom_rep.dat'.
Finished reading report definition file successfully.
Simulation (DESIGN OUT1 1) DESIGN OUT1 1 Pulse Typ Reflection
E- ERROR(SPSIMS-57): hspice_lis2sim.pl failed to translate waveforms.lis in sigxp.run/case0/sim1.
E- Simulation (DESIGN OUT1 1) DESIGN OUT1 1 Pulse Typ Reflection Failed
问题是否出在Hspice上啊，老师。

doltbird

回复 1# alansandy0923


   你的hspice跑完了么？ 如果Hspice没有问题，应该有个 .tr0的文件，用hspice的scope可以直接看这个文件。如果这个结果是正确的，那就是cadence的问题了。

alansandy0923

回复 2# doltbird


    感谢老师的答复，昨天我用hspice2010跑的，卸载了2010后，我按照了个2008版本的，在hspice中出现

Google了下，说我的hspice的lincese有问题，
我的hspice环境变量设置为：
1：变量名：AVANTD_LICENSE_FILE
    变量值：C:\synopsys\Hspice_A-2008.03\license.dat
2：变量名：SNPSLMD_LICENSE_FILE
     变量值：C:\synopsys\Hspice_A-2008.03\license.dat
老师，是否是我的环境变量设置问题，还是我的lincese有问题啊，
同时，我的hspice已经跑完，也有老师说的.tro文件，

最好跑完后SQ仍出现如下信息：
Command Output Window
Starting new drawing...
Finished loading SigNoise device libraries
Using working device library 'D:/Cadence Project/Cadence_SIIGX_Kit_0p3/Simulation/Hspice_Verify/devices.dml'
Already Placed Circuit
Clearing simulation data for "case0"

last pick:  5503.50  4243.50
Using SigNoise run directory 'D:/Cadence Project/Cadence_SIIGX_Kit_0p3/Simulation/Hspice_Verify/sigxp.run'
Reading report definition file 'D:/Cadence/SPB_16.2/share/pcb/signal/reports.dat'.
Finished reading report definition file successfully.
Standard report 'ComprehensiveForSourceSyncBus' has been replaced.
Reading report definition file 'D:/Cadence/SPB_16.2/share/pcb/signal/custom_rep.dat'.
Finished reading report definition file successfully.
Simulation (DESIGN OUT1 1) DESIGN OUT1 1 Pulse Typ Reflection
E- ERROR(SPSIMS-57): hspice_lis2sim.pl failed to translate waveforms.lis in sigxp.run/case0/sim1.
E- Simulation (DESIGN OUT1 1) DESIGN OUT1 1 Pulse Typ Reflection Failed
跑完后SQ跳出的提示栏位：

老师：是我的hspice的lincese还是sigxplore有问题呢。
麻烦老师了，呵呵。

alansandy0923

回复 2# doltbird


   
老师，怎么用hspice打开.tro文件啊，
tro文件我用记事本打开里面内容为：
00290002000000009601    *                                                      
        03/29/2002      08:17:09 Copyright (C) 1985-2001 by Avant! Corporation.
                           0                                                   
                          1       1       1       1       1       1       1     
  1       1       1       1       1       1       1       1       1       1     
  8       8       8       8       8       8       8       8       8       8     
  8       8       1       1     TIME            0               1               
2               xdesign_icn_ckt.3               xdesign.in1.18  xdesign.in1.19  
xdesign.in1.20  xdesign.in1.21  xdesign.in1.22  xdesign.in1.23  xdesign.out1.18
xdesign.out1.19 xdesign.out1.20 xdesign.out1.21 xdesign.out1.22 xdesign.out1.23
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n.in1.1_19      I(xdesign.in1.v_power_clamp_bus_design.in1.1_20 I(xdesign.in1.v_
ground_clamp_bus_design.in1.1_21                I(xdesign.out1.v_power_bus_desig
n.out1.1_18     I(xdesign.out1.v_ground_bus_design.out1.1_19    I(xdesign.out1.v
_power_clamp_bus_design.out1.1_20               I(xdesign.out1.v_ground_clamp_bu
s_design.out1.1_21              I(xdesign.in1.x_stimulus.v_enable_off           
I(xdesign.in1.x_stimulus.v_input_inactive       I(xdesign.out1.x_stimulus.v_5   
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