- 积分
- 27
- 兑换点
- 点
- 声望度
-
- 金钱
- 元
- 银行存款
- 元
- 贡献度
-
- 精华
|
在仿真log中提示
** Error **: DDRx simulation halted; user specified time limit was reached for this net!
Calculation of SI delay times for type: W1_Typ; for pin: U9.G8&H8; for net: DDR_CK; position: Rank(1,1);
Compare against driver pin: U8.K2&K1;
Thresholds: RiseVmeas = 0.000, FallVmeas = 0.000, LowAc = -1.080, HiAc = 1.080
** Info **: Simulation of this net failed!
Calculation of skew time for type: W1_Typ; for pin: U9.J7; for net: DQS0; position: Rank(1,1);
Compare against clk pin: U9.G8&H8; clk net: DDR_CK
Using thresholds: strobe Vref = 0.900, clk Vref = 0.000
Checking waveform around the point: 0.057ns
Checking waveform around the point: 0.090ns with shifting to 5.788ns because skew is more than 1/2 of clock period
** Error **: Multi-threshold for the clk net is found!!! Calculation of skew time is cancelled for this net!
不知道怎么修改,请大家帮忙看看。
|
|