请教:allegro16.6导网表出错，原理图中不知如何修改？

tianshifu0716

ERROR(SPMHNI-88): Device file was parsed, errors were detected. Run netin in s~
yntax check mode for detailed error report.

!r_0603!\'60_300mr\'; fb16
                   ^
ERROR(SPMHNI-88): Device file was parsed, errors were detected. Run netin in s~
yntax check mode for detailed error report.
-------------------------------------------------------------------------------
!l0603!\'60_300mr\'; fb17
                  ^
ERROR(SPMHNI-88): Device file was parsed, errors were detected. Run netin in s~
yntax check mode for detailed error report.
-------------------------------------------------------------------------------
!l0603!\'60_300mr\'; fb18
                  ^
ERROR(SPMHNI-88): Device file was parsed, errors were detected. Run netin in s~
yntax check mode for detailed error report.
-------------------------------------------------------------------------------
!l0603!\'60_300mr\'; fb19
                  ^
ERROR(SPMHNI-88): Device file was parsed, errors were detected. Run netin in s~
yntax check mode for detailed error report.
-------------------------------------------------------------------------------
请教各们高高手，在allegro16.6导入网表时出这种提示的错误，不知如何解决！还只是第一步，原理图检验的导入，问题在的原理图的这类FB17 ,FB18,FB19当中，问题是这类原件在allegro15.5中的PCB导入网表是没有问题的。把PCB改为用16.6就出这种现象，郁闷啊????

tianshifu0716

原理图中的原件的value是这样的

力劈玄黄

楼主回来了，声明一下，不要乱发，我是来混经验的，你们知道这帖子不早发，非在我这里发吗？既然我先发了，看过的可以不看，不过别捣乱！