wg2000.5 and wg2002[求助]

kjhghgn

请教wg2000.5 and wg2002区别？？1！

ricky2008

This release of the Library Manager contains new features that improve performance and increase productivity. The following describes these features. Please review these descriptions carefully and determine any impact these new features may have on your design flow.


WG2002

Reusable Blocks

The 揜eusable Block?(RB) feature enables the user to create 揷ircuitry blocks?in both the schematic and layout files and store them in the Central Library (CL) for future use. The user designs the circuitry block in both the schematic and layout areas, verifies the circuits through tools provided then stores them in the CL. This functionality provides the user the ability to utilize known good circuitry with the simplicity of placing a single element in a design. These Reusable Blocks would be available to any user who has access to the central library where the RB's are stored and a Reusable Block license.

DXF Export from Cell Editor

Allows for export of cell data to a DXF file.

DXF Import into Padstack Editor
Allows for import of DXF data into custom pads and custom drill symbols.


Prevention of Duplicate Cells in Central Library

Option to disallow creation of duplicate cell names in a Central Library by use of an environmental variable.

Polygon Fill option for Silkscreen and Assembly Layers in Cell Editor
Polygons on the Silkscreen and Assembly layers can now be filled in the Cell Editor

Grid Settings on Per Cell Basis
The Routing and Placement grid settings defined in the Editor Control dialog are now saved on a per cell basis in the Cell Editor.

Additional Plane Shape Options Enabled in Cell Editor

Plane Shapes in the Cell Editor now have the same option settings as in the PCB design editor:  Route Obstruct, Hatch Spacing, Hatch Width, Hatch Pattern has been enabled.

Copyright Mentor Graphics Corporation 1999-2002.

ricky2008

This release of DesignView contains new features that improve performance and increase productivity. The following describes these features. Please review these descriptions carefully and determine any impact these new features may have on your design flow.


Product Versions

DesignView was certified using the following version of tools:


FPGA Advantage 5.4
ModelSim SE/PE 5.7
LeonardoSpectrum 2002e.16
Synplify/Synplify Pro 7.1A
Tau 3.0
Actel Designer R1-2002 SP2
Altera MAX+PLUS II 10.21
Altera Quartus II 2.1 SP1
Xilinx Project Navigator ISE 5.1i

WG2002 Spac 3


Boardlink - IOBANK Fracturing Scheme - Boardlink has added a new fracturing scheme for using Boardlink in conjunction with the Fractured Symbol Partitioner. The IOBANK fracturing scheme uses the IOBANK information from the vendor pin file to fracture the pins of the FPGA. For vendors who don't supply IOBANK information, Boardlink will use the default Functional or Physical fracturing method.

Boardlink - IOBANK Power Box Fracturing Scheme - In conjunction with the IOBANK fracturing scheme is the IOBANK Power box scheme which tells Boardlink to create power and ground fractures for the supply pins listed with IOBANK information.

DesignView/DMS Integration - DesignView has been enhanced to work with Mentor Graphic's DMS product.


Boardlink Enhanced Support for Existing Fractured Parts and Symbols - Boardlink has been enhanced to use fractured symbols and libraries that already exist and or are supplied by a 3rd party and have not been created/partitioned by FSP.

WG2002 SPac 2

Fractured Symbol Partitioner - DesignView now includes a spreadsheet style editor that allows users to fracture large pin count devices into smaller, easier to use, symbols. PDB's are automatically generated for the new device as the fractures are generated. The functionality is available on the Place Device dialog, the Tools pulldown menu and the Tools pulldown menu from inside the Symbol Editor.

Enhanced BoardLink - BoardLink has been enhanced to work with the Fractured Symbol Partitioner.

Equivalent Part Number - A new property 'Equiv Part Number', has been added in support of the Fractured Symbol Partitioner (FSP) to enable the user to map FSP-generated devices to existing Part Numbers in order to maintain corporate part name and numbering conventions for bills of material. When set to yes, cdb2bom will look for the property 'Equiv Part Number' on the part. If the property exists and has a value, cdb2bom will use this property in place of any existing 'Part Number' property in the BOM report.

WG2002 SPac 1

FPGA Advantage Constraint Passing - DesignView now allows the user to pass constraint information from the FPGA Type block into FPGA Advantage. The constraint file shown in FPGA Advantage would then be used for both synthesis and place and route.


WG2002

PCB Design Centric Flow Enhancements - DesignView provides a Design Centric Flow into Expedition PCB which involves enhancements  to facilitate `Anticipated next-step integration' or `Point and Shoot' for the downstream processes of Expedition PCB and Signal Vision respectively.
This includes the moving of PCB related operations to the hierarchy and integration tabs, and the integration to tools such as the CAM output manager, and Signal Vision.

Tau 3.0 Compatibility - DesignView has been enhanced to work with the Tau 3.0 tool.

Block Instance Name Display - DesignView has a new setting in the Active Configuration Settings dialog called 揇isplay Instance Names in Hierarchy Browser? Turning on this option does two things. First, in the hierarchy display, the instance names of each block in the hierarchy are shown next to the block name. Opening a block from the hierarchy tab in this mode automatically opens the schematic in instance edit mode. Second, instance names on hierarchical blocks are made visible in the schematic, and cannot be turned off (either by selecting Edit>roperties, or by using Text Overrides.).

New `FPGA' Block Type - DesignView has a new block view type called `FPGA'. This is used to create and seed a new FPGA Advantage environment for each FPGA in the design. Opening or pushing into this block type will start FPGA Advantage on the  FPGA Advantage design if already created, or will create a new FPGA Advantage design using the interface information from the block.


Boardlink Support for Neutral Pin File - As well as supporting the FPGA vendor's pin lists, Boardlink now supports the use of a `Neutral' pin list format. The neutral pin mapping file will be supported to expand FPGA BoardLink to be used for any LSI design including ASICs and custom LSI.

Boardlink No Bus Option  - Boardlink has added a `No Bus' option which prevents the automatic grouping of bus bits together on the Boardlink schematic. Boardlink leaves each signal as an individual signal if this option is checked.

Autosave Functionality - DesignView now has a configurable 揂utosave?capability.

The 揂utosave?feature will automatically save the schematics being edited during the session after a configurable period of time (in minutes).  The Autosave interval can be set from 1 to 30 minutes in the Tools-Options-Settings dialog. A value of 揘ever?will disable the 揂utosave?function. The default setting is 10 minutes.

Set/Unset Instance Commands - The Set Instance command and a new Unset Instance command are now available on the popup menu when invoked on the schematic background.  This allows for easier access to the commands.  When invoked in a single-instance schematic, the instance path will automatically be set.  When set on a multiple-instantiated schematic, the Set Instance dialog will be issued to allow you to select an instance path.  The Unset Instance will exit the instance-specific editing session.

Select Entire Net Command - New command is available on the popup menu.  When a wire segment is selected, this command will select the entire net.

Schematic File Backup - The schematic backup file is now updated each time the original schematic is saved.

Place Device - The Place Device cell preview has been enhanced to show pin numbers.

PADS Netlist - Enhanced to include cell information from the PDB.

Cadence Allegro Netlist - Enhanced to add NC pins to device files in Allegro netlister and enhanced the backannotation utility to create function names from the symbol_id rather than using the instance name. The symbol_id's are unique across the entire design, so this allows us to support back

annotation with hierarchy. Previously, if we left out the function names for hierarchical designs, allegro would make-up function names and would use them in the back annotation file, but we couldn't map them back to anything.

Copyright Mentor Graphics Corporation 1999-2003