Is there anyone used the EMC control function in Allegro?

sunjiangbo

Hi

I am doing post layout EMI simulation.
I have problem with Clocks, their emission exceeding FCC Class B regulation. I have shielded the clock signal to suppress the emission, but simulation results are same.
There is no change in EMI results. Can any one suggest how to overcome this? I know that SQSI does single net EMI simulation only.

Regards

sunjiangbo

Hey, shielding is worth a crap. If you insist, make sure the shielding has
a good common ground. Do not have several different ground. This will
worsen the problem. Also have several ground plane on the circuit board
and sandwich the board with groud planes. And make sure your clock circuit
does not generate edy current. (I know you are doing post-layout, but you
may
be able to sneek in a few ground planes.)


But most importantly, you need to decouple the line.
You need to make sure that frequency you are fighting is the harmonic
frequency of the clock. Sielding only works for low frequency. You need
to use the ferrite chips to combat the frequency. You have to
observe the characteristic curve of reactance vs. resistance over frequency
to select the right the ferrite beads.

It seems like you need the broad band filter. I am also assuming you are
trying to
clean out the digital signal, since this is the clock you are talking about.

Use your oscilloscope to see the clock signal is clean. If you need to
attenuate,
you can with decoupling circuit using ferrite beads. You can use Spice or
SpectraQuest
to simulate before you can build a circuit.

The detail is still sketchy, but what fequency are you fighting?

Is it just one frequency or several frequency?
What is the dB on the spectrum?


I am in San Jose working for a company that makes ferrite beads, ceramic
caps,
and coupling chips. So if this is a major project, I can be of some
assistance to you.

EMI can jump all over. It may not be coming from your clock circuit. It
may be caused
by the ripple some where in your cicuit. So I suggest using a high speed
oscilloscope to
see how clean your outputs are on your circuit.

This is a heavy subject. You can go to Taiyo Yuden, TDK, Murata, and
Ferrite website,
for more information.

Good luck






Hi

I am doing post layout EMI simulation.
I have problem with Clocks, their emission exceeding FCC Class B regulation.
I have shielded the clock signal to suppress the emission, but simulation
results are same.
There is no change in EMI results. Can any one suggest how to overcome this?
I know that SQSI does single net EMI simulation only.

Regards

Please include this line when replying to this message:

sunjiangbo

Hi,
EMI is very trouble. Add ferrite beads and decoupling cap. is a good idea.
You must thinking about your function of your circuit. What's the frequency of the clock ? Does it need impedance control ? If the impedance is not correctly. The clock may be decreased or noisy. How about your shielding ? Is it closed enough to the clock trace ? Also the clock trace should be as short as possible. To reduce the EMI source is better than to add shielding to a EMI device.